Implementation of very high radix division in FPGAs

A new approach in multiplication-based dividers for FPGAs is proposed. It relies on very high radix algorithms with prescaling of divisor and dividend. The required multiplications (prescale factor computations, divisor prescaling, dividend prescaling, and the division main iteration) are performed using a simplified version of a multiply-add fused unit, which integrates well into the FPGA specific structure. It is shown that the proposed implementation uses a small number of DSP blocks (three for IEEE simple precision, five for IEEE double precision and eight for IEEE quad precision for Spartan 6 devices), in order to perform the division.