A novel spatially configurable differential interface for an electronic system prototyping platform

Abstract This paper presents complete and detailed circuit design, and the first experimental validation of a previously proposed spatially configurable differential interface that was designed to support current mode logic (CML) on a reconfigurable electronic system prototyping platform. The physical and electrical constraints of CML interfaces are described, and an architecture is proposed for transmitting differential signals between two different integrated circuits (ICs) deposited on the prototyping platform surface. The proposed implementation has been validated in a test-chip using a mature 0.18 μ m CMOS technology. Measurements on the test-chip show that the spatially configurable differential interface can operate at a speed of up to 2.5 Gbps.

[1]  William J. Dally,et al.  CMOS high-speed I/Os - present and future , 2003, Proceedings 21st International Conference on Computer Design.

[2]  Yves Blaquière,et al.  A spatially reconfigurable fast differential interface for a wafer scale configurable platform , 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

[3]  Steven Brebels,et al.  Efficient Link Architecture for On-Chip Serial links and Networks , 2006, 2006 International Symposium on System-on-Chip.

[4]  Y. Blaquiere,et al.  An active reconfigurable circuit board , 2008, 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference.

[5]  Nadia Nedjah,et al.  Modern development methods and tools for embedded reconfigurable systems: A survey , 2010, Integr..

[6]  Yves Blaquière,et al.  Digital signal propagation on a wafer-scale smart active programmable interconnect , 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

[7]  Payam Heydari,et al.  Design of ultrahigh-speed low-voltage CMOS CML buffers and latches , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Yves Blaquière,et al.  Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated Circuit , 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

[9]  Y. Blaquiere,et al.  An interconnection network for a novel reconfigurable circuit board , 2008, 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference.