Parallel Algorithms for VLSI Layout Verification

Layout verification determines whether the polygons that represent different mask layers in the chip conform to the technology specifications. Commercial layout verification programs can take tens of hours to run in the flattened representations for large designs. It is therefore desirable to run the DRC problem in parallel to reduce the runtimes. Also, the memory requirements of large chips are such that the entire chip description may not fit in the memory of a single workstation; hence, parallel processing allows one to distribute the memory requirements of the problem across multiple processors. In this paper, we will present a parallel implementation of a design-rule-checking program called ProperDRC which is implemented on top of the ProperCAD environment. ProperDRC has two novel contributions over previous work. First, it is portable across a large number of multiprocessor platforms, including shared memory multiprocessors, message-passing distributed memory multiprocessors, and hybrid architectures comprised of uni- and multiprocessor workstations connected by a network. Second, ProperDRC is able to exploit multiple levels of parallelism. It can utilize data parallelism, task parallelism, or a simultaneous combination of the two types of parallelism to perform DRC operations concurrently on a multiprocessor architecture. This paper presents specifics of the implementation of ProperDRC, provides an analysis of the methods used to obtain parallelism, addresses load balancing issues, and reports on experimental results on various benchmark circuits.