A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks

On-Chip Networks (OCNs) have been proposed to solve the complex on-chip communication problems. In Very Deep-Submicron era, OCN will also be affected by faults in chip due to technologies shrinking. Many researches focused on fault detection and diagnosis in OCN systems. However, these approaches didn’t consider faulty OCN system recovery. This paper proposes a scalable built-in self-recovery (BISR) design methodology and corresponding Surrounding Test Ring (STR) architecture for 2D-mesh based OCNs to extend the work of diagnosis. The BISR design methodology consists of STR architecture generation, faulty system recovery, and system correctness maintenance. For an n×n mesh, STR architecture contains one controller and 4n test modules which are formed as a ring-like connection surrounding the OCN. Moreover, these test modules generate test patterns for fault diagnosis during warm-up time. According to these diagnosis results, the faulty system is recovered. Finally, this paper proposes a fault-tolerant routing algorithm, Through-Path Fault-Tolerant (TP-FT) routing, to maintain the correctness of this faulty system. In our experiments, the proposed approach can reduce 68.33∼79.31% unreachable packets and 4.86∼23.6% latency in comparison with traditional approach with 8.48∼13.3% area overhead.

[1]  Luca Benini,et al.  Networks on chip: a new paradigm for systems on chip design , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[2]  Wen-Chung Shen,et al.  Fault-tolerant router with built-in self-test/self-diagnosis and fault-isolation circuits for 2D-mesh based chip multiprocessor systems , 2009, 2009 International Symposium on VLSI Design, Automation and Test.

[3]  Alexandre M. Amory,et al.  A scalable test strategy for network-on-chip routers , 2005, IEEE International Conference on Test, 2005..

[4]  Partha Pratim Pande,et al.  BIST for network-on-chip interconnect infrastructures , 2006, 24th IEEE VLSI Test Symposium.

[5]  Ge-Ming Chiu,et al.  Fault-Tolerant Routing Algorithm for Meshes without Using Virtual Channels , 1998, J. Inf. Sci. Eng..

[6]  Johnny Öberg,et al.  Toward a Scalable Test Methodology for 2D-mesh Network-on-Chips , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[7]  Alexandre M. Amory,et al.  Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism , 2006, Eleventh IEEE European Test Symposium (ETS'06).

[8]  Jeong-Gun Lee,et al.  Implications of Rent's Rule for NoC Design and Its Fault-Tolerance , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[9]  Xiaoqing Wen,et al.  VLSI Test Principles and Architectures , 2006 .

[10]  Raimund Ubar,et al.  Test Configurations for Diagnosing Faulty Links in NoC Switches , 2007, 12th IEEE European Test Symposium (ETS'07).

[11]  Jie Wu,et al.  A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model , 2003, IEEE Trans. Computers.

[12]  Radu Marculescu,et al.  Application-specific buffer space allocation for networks-on-chip router design , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[13]  Zainalabedin Navabi,et al.  A concurrent testing method for NoC switches , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[14]  ChalasaniSuresh,et al.  Fault-Tolerant Wormhole Routing Algorithms for Mesh Networks , 1995 .

[15]  Suresh Chalasani,et al.  Fault-Tolerant Wormhole Routing Algorithms for Mesh Networks , 1995, IEEE Trans. Computers.

[16]  R. Ubar,et al.  An External Test Approach for Network-on-a-Chip Switches , 2006, 2006 15th Asian Test Symposium.

[17]  Raimund Ubar,et al.  Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips , 2009, IET Comput. Digit. Tech..

[18]  Xiaoqing Wen,et al.  VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon) , 2006 .

[19]  Qiang Xu,et al.  Re-Examining the Use of Network-on-Chip as Test Access Mechanism , 2008, 2008 Design, Automation and Test in Europe.

[20]  Alain Greiner,et al.  A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[21]  Érika F. Cota,et al.  Constraint-Driven Test Scheduling for NoC-Based Systems , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.