A VCO jitter performance comparison of frequency synthesizer with analog-HDL and SPICE modeling

We compared jitter performance of a VCO in PLL of a frequency synthesizer with analog-HDL and SPICE modeling. In this paper, the time domain performance comparison accomplished by an AHDL model and a SPICE model which can be used to predict the VCO jitter. All of the jitter cannot be easily simulated at Tr-level, which requires of lot of time to simulate the overall system. We show the jitter model of VCO in PLL of frequency synthesizer by analog-HDL and SPICE modeling which require much less time to simulate the phase noise of a VCO. The comparison results give the relationship of AHDL and SPICE model, which are used to design mixed-signal circuits.