论文信息 - Design and implementation of CDR and SerDes for high speed optical communication networks using FPGA

Design and implementation of CDR and SerDes for high speed optical communication networks using FPGA

In this paper, we design and implement the Clock and Data-Recovery (CDR) with Serializer/Deserializer (SerDes) on Spartan SP605 supports a data-rate up-to 3.2 Gbps with locking time less-than 5×10<sup>-7</sup> s, and bit-error rate less-than 10<sup>-10</sup>.

Hassan Mostafa | Tawfik Ismail | Kareem Ismail

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