Network-on-Chips on 3-D ICs: Past, Present, and Future

Abstract Interconnects have become the chief bottleneck in today’s era of chip design. Along the road of interconnect evolution, Network-on-Chips (NoCs) have emerged as a structured and scalable solution for connecting computational elements on a very large scale integration chip. Also, with the deep-submicron technology allowing integration of billions of transistors, chips have grown very complex and large in size. The global wire-length problem was addressed with the integration of devices in the third dimension (3-D). The combination of 3-D integration and a scalable interconnect, like NoCs, promise to revolutionize design for Chip Multi-processors, System-on-chips, and System-in-package. This paper surveys on all the advancements in 3-D NoCs.

[1]  Hannu Tenhunen,et al.  A study of Through Silicon Via impact to 3D Network-on-Chip design , 2010, 2010 International Conference on Electronics and Information Engineering.

[2]  Luca Benini,et al.  Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  Jianhao Hu,et al.  De Bruijn graph based 3D Network on Chip architecture design , 2009, 2009 International Conference on Communications, Circuits and Systems.

[4]  Kevin Skadron,et al.  Temperature-aware microarchitecture , 2003, ISCA '03.

[5]  Chita R. Das,et al.  A novel dimensionally-decomposed router for on-chip communication in 3D architectures , 2007, ISCA '07.

[6]  Fredrik Larsson,et al.  Simics: A Full System Simulation Platform , 2002, Computer.

[7]  Luca Benini,et al.  Synthesis of networks on chips for 3D systems on chips , 2009, 2009 Asia and South Pacific Design Automation Conference.

[8]  Bhabani Shankar Prasad Mishra,et al.  Parallel Computing Environments: A Review , 2011 .

[9]  Amruta S. Kharate,et al.  Jpeg Image Compression Using Fpga , 2014 .

[10]  Muhannad S. Bakir,et al.  3D Integrated Circuits: Liquid Cooling and Power Delivery , 2009 .

[11]  Luca Benini,et al.  Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs , 2003, Proceedings 21st International Conference on Computer Design.

[12]  Akram Ben Ahmed,et al.  Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC , 2010, 2010 International Conference on Broadband, Wireless Computing, Communication and Applications.

[13]  Hannu Tenhunen,et al.  3-D memory organization and performance analysis for multi-processor network-on-chip architecture , 2009, 2009 IEEE International Conference on 3D System Integration.

[14]  Luca Benini,et al.  Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[15]  Dean M. Tullsen,et al.  Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

[16]  Bill Lin,et al.  Design of application-specific 3D Networks-on-Chip architectures , 2008, 2008 IEEE International Conference on Computer Design.

[17]  Hideharu Amano,et al.  Tightly-Coupled Multi-Layer Topologies for 3-D NoCs , 2007, 2007 International Conference on Parallel Processing (ICPP 2007).

[18]  Fabien Clermidy,et al.  A fully-asynchronous low-power framework for GALS NoC integration , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[19]  Kunle Olukotun,et al.  The case for a single-chip multiprocessor , 1996, ASPLOS VII.

[20]  C.C. Liu,et al.  Crosstalk reduction in mixed-signal 3-D integrated circuits with interdevice layer ground planes , 2005, IEEE Transactions on Electron Devices.

[21]  J.W. Joyner,et al.  A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC) , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

[22]  Said F. Al-Sarawi,et al.  A Review of 3-D Packaging Technology , 1998 .

[23]  L. Benini,et al.  Designing Application-Specific Networks on Chips with Floorplan Information , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[24]  Gabriel H. Loh,et al.  Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors , 2007, 2007 IEEE 13th International Symposium on High Performance Computer Architecture.

[25]  Martin Burtscher,et al.  Bridging the processor-memory performance gap with 3D IC technology , 2005, IEEE Design & Test of Computers.

[26]  Andreas Hansson,et al.  A Unified Approach to Mapping and Routing in a Combined Guaranteed Service and Best-Effort Network-on-Chip Architecture , 2005 .

[27]  Yuzhuo Fu,et al.  Thermal management via task scheduling for 3D NoC based multi-processor , 2010, 2010 International SoC Design Conference.

[28]  Dhiraj K. Pradhan,et al.  Reliable network-on-chip based on generalized de Bruijn graph , 2007, 2007 IEEE International High Level Design Validation and Test Workshop.

[29]  Ding-Ming Kwai,et al.  Floorplanning 1024 cores in a 3D-stacked networkon- chip with thermal-aware redistribution , 2010, 2010 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems.

[30]  Mohammad Arjomand,et al.  Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs , 2010, 2010 23rd International Conference on VLSI Design.

[31]  Sung Kyu Lim,et al.  Physical design for 3D system on package , 2005, IEEE Design & Test of Computers.

[32]  Li Shang,et al.  Thermal Modeling, Characterization and Management of On-Chip Networks , 2004, 37th International Symposium on Microarchitecture (MICRO-37'04).

[33]  Sachhidh Kannan,et al.  Highly-scalable 3D CLOS NOC for many-core CMPs , 2010, Proceedings of the 8th IEEE International NEWCAS Conference 2010.

[34]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[35]  Kaushik Roy,et al.  Stochastic interconnect modeling, power trends, and performance characterization of 3-D circuits , 2001 .

[36]  Hannu Tenhunen,et al.  BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels , 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

[37]  Jiang Peng,et al.  Through-silicon via (TSV) capacitance modeling for 3D NoC energy consumption estimation , 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

[38]  Axel Jantsch,et al.  Scalability of network-on-chip communication architecture for 3-D meshes , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[39]  Luca Benini,et al.  A Method for Integrating Network-on-Chip Topologies with 3D ICs , 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

[40]  Cheng-Shang Chang,et al.  Performance guarantees in communication networks , 2000, Eur. Trans. Telecommun..

[41]  Ahmed Amine Jerraya,et al.  An efficient hierarchical router for large 3D NoCs , 2010, Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping.

[42]  Charles Addo-Quaye,et al.  Thermal-aware mapping and placement for 3-D NoC designs , 2005, Proceedings 2005 IEEE International SOC Conference.

[43]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[44]  Hannu Tenhunen,et al.  Research and practices on 3D networks-on-chip architectures , 2010, NORCHIP 2010.

[45]  R. Guerrieri,et al.  3D Contactless communication for IC design , 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

[46]  Luca Benini,et al.  A low-overhead fault tolerance scheme for TSV-based 3D network on chip links , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[47]  Steven M. Nowick,et al.  Robust interfaces for mixed-timing systems with application to latency-insensitive protocols , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[48]  Luca Benini,et al.  Developing Mesochronous Synchronizers to Enable 3D NoCs , 2008, 2008 Design, Automation and Test in Europe.

[49]  Jianhao Hu,et al.  MSNS: A Top-Down MPI-Style Hierarchical Simulation Framework for Network-on-Chip , 2009, 2009 WRI International Conference on Communications and Mobile Computing.

[50]  Wenhua Dou,et al.  Analysis of communication delay bounds for network on chips , 2009, 2009 Asia and South Pacific Design Automation Conference.

[51]  Yuan Xie,et al.  3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC) , 2009, 2009 IEEE International Conference on 3D System Integration.

[52]  David A. Wood,et al.  Managing Wire Delay in Large Chip-Multiprocessor Caches , 2004, 37th International Symposium on Microarchitecture (MICRO-37'04).

[53]  An-Yeu Wu,et al.  Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems , 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.

[54]  William J. Dally,et al.  Digital systems engineering , 1998 .

[55]  Mahmut T. Kandemir,et al.  Design and Management of 3D Chip Multiprocessors Using Network-in-Memory , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[56]  Hideharu Amano,et al.  Three-Dimensional Layout of On-Chip Tree-Based Networks , 2008, 2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008).

[57]  Chita R. Das,et al.  MIRA: A Multi-layered On-Chip Interconnect Router Architecture , 2008, 2008 International Symposium on Computer Architecture.

[58]  Chita R. Das,et al.  Design and analysis of an NoC architecture from performance, reliability and energy perspective , 2005, 2005 Symposium on Architectures for Networking and Communications Systems (ANCS).

[59]  Katsuyuki Sakuma,et al.  Three-dimensional silicon integration , 2008, IBM J. Res. Dev..

[60]  Luca Benini,et al.  Networks on chips - technology and tools , 2006, The Morgan Kaufmann series in systems on silicon.

[61]  Partha Pratim Pande,et al.  Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation , 2009, IEEE Transactions on Computers.

[62]  Charles Clos,et al.  A study of non-blocking switching networks , 1953 .

[63]  Alyssa B. Apsel,et al.  On-Chip Optical Technology in Future Bus-Based Multicore Designs , 2007, IEEE Micro.

[64]  Rajiv V. Joshi,et al.  Three dimensional CMOS devices and integrated circuits , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[65]  Assaf Shacham,et al.  Maximizing GFLOPS-per-Watt : High-Bandwidth , Low Power Photonic On-Chip Networks , 2006 .

[66]  Ben A. Abderazek,et al.  Advanced Design Issues for OASIS Network-on-Chip Architecture , 2010, 2010 International Conference on Broadband, Wireless Computing, Communication and Applications.

[67]  Wei Zhang,et al.  A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip , 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

[68]  Fabien Clermidy,et al.  A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip , 2008, IEEE Journal of Solid-State Circuits.

[69]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[70]  Rene L. Cruz,et al.  A calculus for network delay, Part I: Network elements in isolation , 1991, IEEE Trans. Inf. Theory.

[71]  Wenhua Dou,et al.  From 2D to 3D NoCs: A case study on worst-case communication performance , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[72]  Iraklis Anagnostopoulos,et al.  A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple Vdd , 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

[73]  Luca P. Carloni,et al.  Networks-on-chip in emerging interconnect paradigms: Advantages and challenges , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[74]  Norman P. Jouppi,et al.  Cacti 3. 0: an integrated cache timing, power, and area model , 2001 .

[75]  Luca Benini,et al.  3D NoCs — Unifying inter & intra chip communication , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[76]  Wai-Kai Chen,et al.  The VLSI Handbook , 2000 .

[77]  Doug Burger,et al.  An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches , 2002, ASPLOS X.

[78]  Sung Kyu Lim,et al.  Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs , 2010, SLIP '10.

[79]  Bill Lin,et al.  A Layer-Multiplexed 3D On-Chip Network Architecture , 2009, IEEE Embedded Systems Letters.

[80]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[81]  John M. Cohn,et al.  Managing power and performance for system-on-chip designs using Voltage Islands , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

[82]  Zhonghai Lu,et al.  Feasibility analysis of messages for on-chip networks using wormhole routing , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[83]  Chita R. Das,et al.  A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[84]  D. E. Goldberg,et al.  Genetic Algorithms in Search , 1989 .

[85]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[86]  Luca Benini,et al.  SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[87]  Yehea Ismail,et al.  3D/TSV enabling technologies for SOC/NOC: Modeling and design challenges , 2010, 2010 International Conference on Microelectronics.

[88]  Luca Benini,et al.  Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow , 2007, Nano-Net.

[89]  William J. Dally,et al.  Research Challenges for On-Chip Interconnection Networks , 2007, IEEE Micro.

[90]  Eric Beyne,et al.  Impact of 3D design choices on manufacturing cost , 2009, 2009 IEEE International Conference on 3D System Integration.

[91]  Xiaowei Li,et al.  Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[92]  Yangdong Deng,et al.  2.5D system integration: a design driven system implementation schema , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).