Effect of Different Nano Meter Technology Based FPGA on Energy Efficient UART Design

In this paper, the main aim of authors is to design UART that is implemented on Xilinx ISE Design 14.1 and results were tested on Virtex-4 90nm FPGA, Virtex-5 65nm FPGA and Virtex-6 40nm FPGA. For 90nm FPGA, device used is Virtex-4, part name is xc4vfx12, package used is sf363, and it is working on −12 speed grade at an ambient temperature of 50.0 °C. For 65nm FPGA, device used is Virtex-5, part name-xc5vlx20t, package used is ff323, and it is working on −2 speed grade at an ambient temperature of 50.0 °C. For 40nm FPGA, device used is Virtex-6, part name is xc6vlx75t, package used is ff484, and it is working on −3 speed grade at an ambient temperature of 50.0 °C. In this paper, UART code is written in Verilog language and power is analyzed for 65nm, 90nm and 40nm technology based FPGA.

[1]  Tanesh Kumar,et al.  Performance Evaluation of FIR Filter After Implementation on Different FPGA and SOC and Its Utilization in Communication and Network , 2017, Wirel. Pers. Commun..

[2]  Amanpreet Kaur,et al.  LVCMOS based energy efficient solar charge sensor design on FPGA , 2014, 2014 IEEE 6th India International Conference on Power Electronics (IICPE).

[3]  Bishwajeet Pandey,et al.  HSTL based low power thermal aware adder design on 65nm FPGA , 2015, 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom).

[4]  Kartik Kalia,et al.  I2C and HSTL IO Standard Based Low Power Thermal Aware Adder Design on 45nm FPGA , 2015 .

[5]  Bishwajeet Pandey,et al.  GTL based wireless sensor specific energy efficient ALU design on 65nm FPGA , 2015, 2015 International Conference on Signal Processing, Computing and Control (ISPCC).

[6]  B. Pandey,et al.  Pseudo open drain IO standards based energy efficient solar charge sensor design on 20nm FPGA , 2015, 2015 IEEE 11th International Conference on Power Electronics and Drive Systems.

[7]  Bishwajeet Pandey,et al.  SSTL based Low Power Thermal Efficient WLAN Specific 32 bit ALU Design on 28 nm FPGA , 2016 .