Sub-0.25 micron silicon via etching for 3D interconnects

Three-dimensional (3D) interconnects offer the potential of reducing fabrication and performance limitations of future generations of planar integrated circuits (ICs). Etching high aspect ratio submicron vias for inter-wafer connection is one of the key processing metrics for the wafer-level 3D technology platform. The ability to optimize the effects of the process parameters during via etching is vital for the fabrication of emerging hyperintegration technologies. This paper outlines the establishment of reactive ion etching protocols for fabrication of high aspect ratio silicon vias with minimum bowing employing the Bosch process. High aspect ratio submicron via patterns were transferred into silicon substrates using a Unaxis Versalock deep reactive ion etch (DRIE) tool. Through careful optimization of Bosch etch process conditions, successful etching of high aspect ratio (13:1) 200 nm via features was achieved.

[1]  Chih-Kung Lee,et al.  Etching submicrometer trenches by using the Bosch process and its application to the fabrication of antireflection structures , 2005 .

[2]  Jian-Qiang Lu,et al.  Wafer-Level Three-Dimensional Hyper-Integration Technology Using Dielectric Adhesive Wafer Bonding , 2005 .

[3]  G. K. Ho,et al.  High-Q single crystal silicon HARPSS capacitive beam resonators with self-aligned sub-100-nm transduction gaps , 2003 .

[4]  Anna W. Topol,et al.  Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication , 2002, Digest. International Electron Devices Meeting,.

[5]  David J. Monk,et al.  Submicron high-aspect-ratio silicon beam etch , 2001, SPIE Micro + Nano Materials, Devices, and Applications.

[6]  J. Chiao.  Device and Process Technologies for MEMS and Microelectronics II , 2001 .

[7]  J. Lu,et al.  Three-dimensional (3D) ICs: a technology platform for integrated systems and opportunities for new polymeric adhesives , 2001, First International IEEE Conference on Polymers and Adhesives in Microelectronics and Photonics. Incorporating POLY, PEP & Adhesives in Electronics. Proceedings (Cat. No.01TH8592).

[8]  Serrita A. McAuley,et al.  Silicon micromachining using a high-density plasma source , 2001 .

[9]  Xin Zhang,et al.  Anisotropic silicon trenches 300–500 μm deep employing time multiplexed deep etching (TMDE) , 2001 .

[10]  Kaustav Banerjee,et al.  Interconnect limits on gigascale integration (GSI) in the 21st century , 2001, Proc. IEEE.

[11]  K. Warner,et al.  Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[12]  K. Kano,et al.  Improvement of Si/SiO/sub 2/ mask etching selectivity in the new D-RIE process , 2001, Technical Digest. MEMS 2001. 14th IEEE International Conference on Micro Electro Mechanical Systems (Cat. No.01CH37090).

[13]  R. P. Kraft,et al.  Wafer Bonding Using Dielectric Polymer Thin Films in 3D Integration , 2001 .

[14]  K. W. Lee,et al.  Three-dimensional shared memory fabricated using wafer stacking technology , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[15]  F. Ayazi,et al.  High aspect-ratio combined poly and single-crystal silicon (HARPSS) MEMS technology , 2000, Journal of Microelectromechanical Systems.

[16]  Y. Feurprier,et al.  High aspect ratio SiO2 etching with high resist selectivity improved by addition of organosilane to tetrafluoroethyl trifluoromethyl ether , 2000 .

[17]  K. Najafi,et al.  Design and fabrication of high-performance polysilicon vibrating ring gyroscope , 1998, Proceedings MEMS 98. IEEE. Eleventh Annual International Workshop on Micro Electro Mechanical Systems. An Investigation of Micro Structures, Sensors, Actuators, Machines and Systems (Cat. No.98CH36176.

[18]  Janet Hopkins,et al.  The Benefits of Process Parameter Ramping During The Plasma Etching of High Aspect Ratio Silicon Structures , 1998 .

[19]  W. E. Horne,et al.  Reactive ion etching of silicon stencil masks in the presence of an axial magnetic field , 1995 .

[20]  Miko Elwenspoek,et al.  The black silicon method: a universal method for determining the parameter setting of a fluorine-based reactive ion etcher in deep silicon trench etching with profile control , 1995 .

[21]  M. W. Putty.  A Maicromachined vibrating ring gyroscope , 1994 .

[22]  Kevin K. Chan,et al.  Deep trench plasma etching of single crystal silicon using SF6/O2 gas mixtures , 1992 .

[23]  Gottlieb S. Oehrlein,et al.  Study of sidewall passivation and microscopic silicon roughness phenomena in chlorine‐based reactive ion etching of silicon trenches , 1990 .