MIMO 통신 시스템을 위한 심볼 검출기 설계 연구

In this paper, an area-efficient architecture of symbol detector is proposed for MIMO communication systems with two transmit and receive antennas. The proposed symbol detector was designed in hardware description language (HDL) and implemented with Xilinx Virtex-5 FPGA. With the proposed architecture, the number of slices for the processor is 61520 and the number of DSP48s (dedicated multiplier) is 52, which are reduced by 24.2% and 85.3%, respectively, compared with the conventional architecture.