Modeling Mutual Coupling Capacitance Effects of Package RDL to Chip on Radio Frequency ICs

As technology continues to scale, radio frequency (RF) applications are moving towards higher frequencies and increased levels of integration. This leads to interconnect wiring effects which impact circuit performance significantly. Chip package coupling is one of the major factors in successfully predicting final product performance. This chip-package interaction is difficult to incorporate into post-layout simulation flow; therefore, it is typically ignored. The most common solution is to use an Electromagnetic (EM) simulator to model package effects for the coupling to chip die. Challenges in EM simulations are time consuming to solve, and difficult to seamlessly integrate into parasitic extraction (PEX) simulation flows. Therefore, PEX accuracy and design automation enablement becomes more critical with the increase in performance, density, complexity and integration in analog mixed signal and radio frequency (RF) designs. A PEX solution is preferred over complicated EM tools for handling highly integrated parasitic networks. A truly comprehensive extraction solution allows design houses to have reliable parasitic analysis to reduce silicon spins and facilitate time-to-market. This paper will describe a methodology of modeling mutual coupling effects between on-chip circuits and the chip package, which enables a post-layout simulation flow with incorporating chip and package interactions simultaneously.PEX technology files provided by foundries do not account for package layer effects on a chip, especially with re-distribution layers (RDL). In this paper, we will describe the methodology used for enabling a PEX deck to account for the mutual coupling effects with both test structures and a circuit in practical applications.