论文信息 - Syntax code analysis and generation for Verilog - 字舞流文

Syntax code analysis and generation for Verilog

In this paper, we present a syntax analyser tool for Verilog programs which can be used as a front end to debugging and program verification tools.

Sofiène Tahar | Mohamed H. Zaki | S. Tahar | M. Zaki

[1] Chris Hankin,et al. Program analysis tools , 1998, International Journal on Software Tools for Technology Transfer.

[2] Szu-Tsung Cheng,et al. Compiling Verilog into Automata , 1994 .

[3] Masahiro Fujita,et al. Program slicing for VHDL , 2002 .

[4] E. M. Clarke,et al. Program Sli ing for VHDL ? , 1999 .

[5] Frank Tip,et al. A survey of program slicing techniques , 1994, J. Program. Lang..

[6] Kenneth L. McMillan,et al. Symbolic model checking , 1992 .

[7] Robert P. Kurshan. Formal verification in a commercial setting , 1997, DAC.

[8] Mohamed H. Zaki Hussein. Syntactic model reduction for hardware verification , 2003 .

[9] Mario Stefanoni. Static analysis for VHDL model evaluation , 1994, EURO-DAC '94.

[10] Steven P. Levitan,et al. Control / Data-Flow Analysis for VHDL Semantic Extraction , 1998, J. Inf. Sci. Eng..

[11] Amr Sabry,et al. Putting Operational Techniques to the Test: A Syntactic Theory for Behavioral Verilog , 1999, HOOTS.

[12] Tiziano Villa,et al. VIS: A System for Verification and Synthesis , 1996, CAV.

[13] Jayaram Bhasker. A Verilog HDL Primer , 1997 .

[14] Ernst-Rüdiger Olderog,et al. Verification of Sequential and Concurrent Programs , 1997, Graduate Texts in Computer Science.

[15] Brian W. Kernighan,et al. The C Programming Language , 1978 .