ESSENTIAL: an efficient self-learning test pattern generation algorithm for sequential circuits

The authors present ESSENTIAL, deterministic automatic test pattern generation algorithm for sequential circuits. By combining reverse time processing over time frames and forward processing within time frames, ESSENTIAL avoids the detrimental a priori determination of a topological path to be sensitized or of a primary output, to which the fault effects have to be propagated. Moreover, the proposed test generation approach fully exploits the beneficial techniques that have successfully been used for combinational circuits by the automatic test pattern generation system SOCRATES. In particular, the authors discuss a learning procedure for global implications not only over reconvergent fanout, but also over time frames as well as static and dynamic unique sensitization techniques. After introducing a couple of intelligent heuristics employed for guiding and supporting the decision-making process, the authors report some preliminary but encouraging experimental results.<<ETX>>

[1]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Alonzo Church,et al.  Introduction to Mathematical Logic , 1991 .

[3]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[4]  J. Paul Roth,et al.  A Heuristic Algorithm for the Testing of Asynchronous Circuits , 1971, IEEE Transactions on Computers.

[5]  Alfred V. Aho,et al.  The Design and Analysis of Computer Algorithms , 1974 .

[6]  M. Ray Mercer,et al.  A Topological Search Algorithm for ATPG , 1987, 24th ACM/IEEE Design Automation Conference.

[7]  Shianling Wu,et al.  A Sequential Circuit Test Generation System , 1985, ITC.

[8]  Ralph Marlett,et al.  EBT: A Comprehensive Test Generation Technique for Highly Sequential Circuits , 1978, 15th Design Automation Conference.

[9]  L. H. Goldstein,et al.  SCOAP: Sandia Controllability/Observability Analysis Program , 1988, 17th Design Automation Conference.

[10]  Michael H. Schulz,et al.  Improved deterministic test pattern generation with applications to redundancy identification , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Michael H. Schulz,et al.  Advanced automatic test pattern generation and redundancy identification techniques , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[12]  Kurt Antreich,et al.  Accelerated Fault Simulation and Fault Grading in Combinational Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Donald B. Johnson,et al.  Finding All the Elementary Circuits of a Directed Graph , 1975, SIAM J. Comput..

[14]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[15]  Prathima Agrawal,et al.  CONTEST: a concurrent test generator for sequential circuits , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[16]  Gordon D. Robinson,et al.  HITEST : Intelligent Test Generation , 1983, ITC.

[17]  Robert E. Tarjan,et al.  Finding Dominators in Directed Graphs , 1974, SIAM J. Comput..

[18]  Ralph A. Marlett.  An Effective Test Generation System for Sequential Circuits , 1986, DAC 1986.

[19]  Vishwani D. Agrawal,et al.  A sequential circuit test generation using threshold-value simulation , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[20]  W.-T. Cheng,et al.  The BACK algorithm for sequential test generation , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.