LFSR-Based Test Generation for Reduced Fail Data Volume

Fail data is collected on a tester to allow defect diagnosis to be carried out. The high volume of fail data that some faulty units produce, and the test application time, motivated the development of procedures for terminating the fail data collection process before it stores the entire fail data for a faulty unit. A procedure for modifying a test set to reduce the fail data volume it produces was developed to complement these approaches, but without considering the constraints of a test data compression method. This article describes a procedure for modifying a stored test set to reduce the fail data volume under a test data compression method where a linear-feedback shift-register is used for on-chip decompression. The constraints of the test data compression method affect the procedure in several important ways. The experimental results for benchmark circuits demonstrate the ability of the procedure to reduce the fail data volume by modifying a stored test set.

[1]  Dimitrios Kagaris,et al.  Using the Berlekamp-Massey algorithm to obtain LFSR characteristic polynomials for TPG , 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

[2]  Brion L. Keller,et al.  OPMISR: the foundation for compressed ATPG vectors , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[3]  Wu-Tung Cheng,et al.  Improved volume diagnosis throughput using dynamic design partitioning , 2012, 2012 IEEE International Test Conference.

[4]  Rohit Kapur,et al.  Fault diagnosis in designs with extreme low pin test data compressors , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[5]  Irith Pomeranz,et al.  Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm , 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

[6]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[7]  Irith Pomeranz,et al.  Test Modification for Reduced Volumes of Fail Data , 2017, ACM Trans. Design Autom. Electr. Syst..

[8]  Srikanth Venkataraman,et al.  POIROT: a logic fault diagnosis tool and its applications , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[9]  Ruifeng Guo,et al.  Enhancing Transition Fault Model for Delay Defect Diagnosis , 2008, 2008 17th Asian Test Symposium.

[10]  Leendert M. Huisman,et al.  Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[11]  R. D. Blanton,et al.  Test-data volume optimization for diagnosis , 2012, DAC Design Automation Conference 2012.

[12]  Bernard Courtois,et al.  Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers , 1992 .

[13]  Janusz Rajski,et al.  Diagnosis with Limited Failure Information , 2006, 2006 IEEE International Test Conference.

[14]  Irith Pomeranz,et al.  A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction , 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

[15]  Nur A. Touba,et al.  Survey of Test Vector Compression Techniques , 2006, IEEE Design & Test of Computers.

[16]  Irith Pomeranz.  LFSR-Based Test Generation for Path Delay Faults , 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Irith Pomeranz.  Computation of Seeds for LFSR-Based Diagnostic Test Generation , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Nilanjan Mukherjee,et al.  Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.

[19]  Neha Goel,et al.  A novel diagnostic test generation methodology and its application in production failure isolation , 2016, 2016 IEEE International Test Conference (ITC).