Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

SRAM-based FPGAs are in-field reconfigurable an unlimited number of times. This characteristic, together with their high performance and high logic density, proves to be very convenient for a number of ground and space level applications. One drawback of this technology is that it is susceptible to ionizing radiation, and this sensitivity increases with technology scaling. This is a first order concern for applications in harsh radiation environments, and starts to be a concern for high reliability ground applications. Several techniques exist for coping with radiation effects at user application. In order to be effective they need to be complemented with configuration memory scrubbing, which allows error mitigation and prevents failures due to error accumulation. Depending on the radiation environment and on the system dependability requirements, the configuration scrubber design can become more or less complex. This paper classifies and presents current and novel design methodologies and architectures for SRAM-based FPGAs, and in particular for Xilinx Virtex-4QV/5QV, configuration memory scrubbers.

[1]  L. Sterpone,et al.  RoRA: a reliability-oriented place and route algorithm for SRAM-based FPGAs , 2005, Research in Microelectronics and Electronics, 2005 PhD.

[2]  M. Caffrey,et al.  A review of Xilinx FPGA architectural reliability concerns from Virtex to Virtex-5 , 2007, 2007 9th European Conference on Radiation and Its Effects on Components and Systems.

[3]  Marisa López-Vallejo,et al.  Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs , 2011, PATMOS.

[4]  K. Chapman SEU Strategies for Virtex-5 Devices , 2010 .

[5]  M. Wirthlin,et al.  SEU-induced persistent error propagation in FPGAs , 2005, IEEE Transactions on Nuclear Science.

[6]  Yanmei Li,et al.  A new approach to detect-mitigate-correct radiation-induced faults for SRAM-based FPGAs in aerospace application , 2000, Proceedings of the IEEE 2000 National Aerospace and Electronics Conference. NAECON 2000. Engineering Tomorrow (Cat. No.00CH37093).

[7]  Massimo Violante,et al.  Multiple errors produced by single upsets in FPGA configuration memory: a possible solution , 2005, European Test Symposium (ETS'05).

[8]  M. Caffrey,et al.  Domain Crossing Errors: Limitations on Single Device Triple-Modular Redundancy Circuits in Xilinx FPGAs , 2007, IEEE Transactions on Nuclear Science.

[9]  Sandi Habinc,et al.  Dynamic Partial Reconfiguration in Space Applications , 2009, 2009 NASA/ESA Conference on Adaptive Hardware and Systems.

[10]  Mike Peattie Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode , 2009 .

[11]  Ken LaBel,et al.  Determining the Best-Fit FPGA for a Space Mission: An Analysis of Cost, SEU Sensitivity,and Reliability , 2007 .

[12]  A. Lesea,et al.  Effectiveness of Internal Versus External SEU Scrubbing Mitigation Strategies in a Xilinx FPGA: Design, Test, and Analysis , 2008, IEEE Transactions on Nuclear Science.

[13]  M. Wirthlin,et al.  Fault Tolerant ICAP Controller for High-Reliable Internal Scrubbing , 2008, 2008 IEEE Aerospace Conference.

[14]  Hui Zhou,et al.  The reliability and availability analysis of SEU mitigation techniques in SRAM-based FPGAs , 2009, 2009 European Conference on Radiation and Its Effects on Components and Systems.

[15]  Jih-Jong Wang,et al.  SRAM based re-programmable FPGA for space applications , 1999 .

[16]  D. Bortolato,et al.  Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs” , 2003 .

[17]  D. C. Wilkinson,et al.  Single Event Upsets correlated with environment , 1994 .

[18]  Sayantan Bhattacharya,et al.  An Adaptive Fault-Tolerant Memory System for FPGA-based Architectures in the Space Environment , 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).

[19]  Gary Swift,et al.  Single-Event Upset (SEU) Results of Embedded Error Detect and Correct Enabled Block Random Access Memory (Block RAM) Within the Xilinx XQR5VFX130 , 2010, IEEE Transactions on Nuclear Science.

[20]  M. Berg,et al.  Course Selection of Integrated Circuits for Space Systems Section V : Example 1 : Trading ASIC and FPGA Considerations for System Insertion , 2009 .

[21]  Suitability of reprogrammable FPGAs in space applications , 2002 .

[22]  Chiara Sandionigi,et al.  A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs , 2011, IEEE Transactions on Computers.

[23]  M. Shea,et al.  CREME96: A Revision of the Cosmic Ray Effects on Micro-Electronics Code , 1997 .

[24]  Chen Wei Tseng,et al.  Correcting Single-Event Upsets in Virtex-II Platform FPGA Configuration Memory , 2007 .

[25]  Barry W. Johnson Design & analysis of fault tolerant digital systems , 1988 .

[26]  Maya Gokhale,et al.  Dynamic reconfiguration for management of radiation-induced faults in FPGAs , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[27]  Sergio D'Angelo,et al.  Evaluation of Single Event Upset Mitigation Schemes for SRAM based FPGAs using the FLIPPER Fault Injection Platform , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[28]  Michael J. Wirthlin,et al.  Estimating TMR Reliability on FPGAs Using Markov Models , 2008 .

[29]  C. Lopez-Ongil,et al.  Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation , 2007, IEEE Transactions on Nuclear Science.

[30]  C. Carmichael,et al.  SEU mitigation testing of Xilinx Virtex II FPGAs , 2003, 2003 IEEE Radiation Effects Data Workshop.

[31]  P. Adell Assessing and Mitigating Radiation Effects in Xilinx FPGAs , 2008 .

[32]  Michael J. Wirthlin,et al.  TMR with More Frequent Voting for Improved FPGA Reliability , 2008, ERSA.

[33]  G Allen,et al.  Assessing and mitigating radiation effects in Xilinx SRAM FPGAs , 2008, 2008 European Conference on Radiation and Its Effects on Components and Systems.

[34]  Gary Swift,et al.  Single-Event Characterization of Multi-Gigabit Transceivers (MGT) in Space-Grade Virtex-5QV Field Programmable Gate Arrays (FPGA) , 2010, 2011 IEEE Radiation Effects Data Workshop.

[35]  Heather M. Quinn,et al.  An Introduction to Radiation-Induced Failure Modes and Related Mitigation Methods For Xilinx SRAM FPGAs , 2008, ERSA.

[36]  Alan D. George,et al.  Reconfigurable fault tolerance: A framework for environmentally adaptive fault mitigation in space , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[37]  K.S. Morgan,et al.  SRAM FPGA Reliability Analysis for Harsh Radiation Environments , 2009, IEEE Transactions on Nuclear Science.

[38]  Gary Swift,et al.  VIRTEX-4 VQ static SEU Characterization Summary , 2008 .

[39]  Gregory Allen Virtex-4VQ dynamic and mitigated single event upset characterization summary , 2009 .

[40]  Gregory Allen Mitigation selection and qualification recommendations for Xilinx Virtex, Virtex-II, and Virtex-4 field programmable gate arrays , 2009 .

[41]  M. Alvarez,et al.  Radiation Hardening of FPGA-Based SoCs through Self-Reconfiguration and XTMR Techniques , 2008, 2008 4th Southern Conference on Programmable Logic.