Simultaneous gate sizing and placement

This paper presents an iterative optimization technique for improving delay in integrated circuits. The basic idea is to perform timing analysis to identify the set of k most-critical paths in the circuit followed by cell resizing and replacement along the critical path set and their neighboring cells. The process is repeated until no further reduction in circuit delay is possible. At the core of this technique lies a mathematical formulation for simultaneous cell sizing and placement subject to timing and position constraints. We show that the resulting problem formulation is a generalized geometric program, which can be solved by solving a sequence of geometric programs. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches which separate gate sizing from gate placement.

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