CMOS scaling beyond 32nm: Challenges and opportunities

This paper explores the challenges and opportunities facing CMOS process generations past the 32 nm technology node. Planar and multiple-gate devices are compared and contrasted. Resistance and capacitance challenges are reviewed in relation to past history and on-going research. Key enhancers such as high-k metal-gate (HiK-MG), substrate and channel orientation, and NMOS and PMOS strain, are discussed in relation to the challenges of the coming transistor generations.