Impact of through-silicon-via scaling on the wirelength distribution of current and future 3D ICs
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In this paper, we investigate the impact of TSV scaling on the wirelength distribution of the 3D ICs. This investigation includes wirelength distribution prediction of 3D ICs for current/future process/TSV technologies, studies on the impact of the design granularity at each process node, the impact of the die count, and the impact of TSV area constraint, and cross-comparison among various 2D and 3D technologies.
[1] Sung Kyu Lim,et al. Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs , 2009, SLIP '09.
[2] Paul D. Franzon,et al. Design automation for a 3DIC FFT processor for synthetic aperture radar: A case study , 2009, 2009 46th ACM/IEEE Design Automation Conference.
[3] J.A. Davis,et al. A three-dimensional stochastic wire-length distribution for variable separation of strata , 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).