Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology

This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back Muller C-elements. Simulation results demonstrate the double-node upset resilience and a 73.0% delay-power-area product saving on average compared with the up-to-date DNURL designs.

[1]  Huaguo Liang,et al.  A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology , 2015, IEICE Trans. Electron..

[2]  Yuanqing Li,et al.  Double Node Upsets Hardened Latch Circuits , 2015, J. Electron. Test..

[3]  Kiamal Z. Pekmestzi,et al.  DONUT: A Double Node Upset Tolerant Latch , 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

[4]  Maryam Shojaei Baghini,et al.  Robust Soft Error Tolerant CMOS Latch Configurations , 2016, IEEE Transactions on Computers.

[5]  Xu Hui,et al.  Circuit and layout combination technique to enhance multiple nodes upset tolerance in latches , 2015, IEICE Electron. Express.

[6]  Sylvain Clerc,et al.  New D-Flip-Flop Design in 65 nm CMOS for Improved SEU and Low Power Overhead at System Level , 2013, IEEE Transactions on Nuclear Science.

[7]  Ken Choi,et al.  High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Huaguo Liang,et al.  A High Performance SEU Tolerant Latch , 2015, J. Electron. Test..

[9]  Massimo Alioto,et al.  Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Ahmad Patooghy,et al.  Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies , 2007, 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07).

[11]  Huaguo Liang,et al.  High-performance, low-cost, and highly reliable radiation hardened latch design , 2016 .

[12]  T.M. Mak,et al.  Built-In Soft Error Resilience for Robust System Design , 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.

[13]  Kostas Tsoumanis,et al.  Delta DICE: A Double Node Upset resilient latch , 2015, 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS).

[14]  Nadziroh Nadziroh,et al.  KONSEP PEMBELAJARAN PKN DALAM MENANAMKAN PENDIDIKAN ANTI KORUPSI SEJAK DINI DISEKOLAH DASAR , 2017 .

[15]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[16]  Cecilia Metra,et al.  High-Performance Robust Latches , 2010, IEEE Transactions on Computers.

[17]  Fabrizio Lombardi,et al.  Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  L. W. Massengill,et al.  Single Event Transients in Digital CMOS—A Review , 2013, IEEE Transactions on Nuclear Science.

[19]  P. E. Dodd,et al.  Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction , 2013, IEEE Transactions on Nuclear Science.

[20]  Yiorgos Tsiatouhas,et al.  Soft error interception latch: double node charge sharing SEU tolerant design , 2015 .

[21]  P. Reviriego,et al.  Reliability Analysis of Memories Suffering Multiple Bit Upsets , 2007, IEEE Transactions on Device and Materials Reliability.