Coverage-driven mixed-signal verification of smart power ICs in a UVM environment

The complexity of integrated circuits is continuously increasing, leading to a growing demand for methodologies that offer comprehensive mixed-signal verification concepts. However, compared to the highly automated verification methodologies in the digital domain, pre-silicon verification in the analog domain usually implies a substantial amount of manual work and computational effort. In order to meet the rising challenges, various attempts were made to extend well-established approaches from the field of digital verification to also enable systematic mixed-signal verification. However, no methodology could be identified that meets our requirements for high reusability and maintainability, tool independence as well as capabilities for functional coverage collection. For this reason, we propose a mixed-signal verification methodology that covers the aforementioned as well as additional aspects required for a successful coverage closure. The presented concept is applied to a smart power application to demonstrate its potential and outline the gained benefits.