With the advent of the great challenge brought by increasing complexity of modern large circuit, a pressing and necessary problem, that is, improving the routability and timing performance, is proposed in front of us. A novel packing algorithm called repack based on enhanced packing attraction function is presented while at the same time an iterative CAD flow tool could provide decreased interconnection resources requirement by applying CLB depopulation at given routing channel width limitation and local congested situations. Experimental results show that, for non-iterative flow, compared to the T-VPack and iRAC, repack can achieve 6.4% and 8.1% improvement respectively in timing performance. However, for iterative flow, when compared to T-VPack, repack has 12.6% and 37.6% improvement in area and routing path width respectively. When compared to iRAC, repack has a 0.9% decrease in area, but it has an improvement of 16.2% in routing path width instead.
[1]
Malgorzata Marek-Sadowska,et al.
Efficient circuit clustering for area and power reduction in FPGAs
,
2002,
TODE.
[2]
Vaughn Betz,et al.
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
,
1999,
FPGA '99.
[3]
Majid Sarrafzadeh,et al.
Routability-Driven Packing: Metrics And Algorithms For Cluster-Based FPGAs
,
2004,
J. Circuits Syst. Comput..
[4]
Ali Akoglu,et al.
MO-Pack: Many-objective clustering for FPGA CAD
,
2011,
2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).
[5]
Majid Sarrafzadeh,et al.
RPack: routability-driven packing for cluster-based FPGAs
,
2001,
ASP-DAC '01.