A sub 100ns 256K DRAM in CMOS III technology

A sub 100ns 256Kb CMOS DRAM with 25μW standby power, 25MHz ripple mode and static column mode data rate will be reported. Channel length is 1μm and the SER is below 0.1%/1KHr.

[1]  S. Kohyama,et al.  A 64Kb CMOS RAM , 1982, 1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  J. Schutz,et al.  A 70ns high density CMOS DRAM , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.