Outstanding Paper Award: Making Shared Caches More Predictable on Multicore Platforms

In safety-critical cyber-physical systems, the usage of multicore platforms has been hampered by problems due to interactions across cores through shared hardware. The inability to precisely characterize such interactions can lead to worst-case execution time pessimism that is so great, the extra processing capacity of additional cores is entirely negated. In this paper, several techniques are proposed and analyzed for dealing with such interactions in the context of shared caches. These techniques are applied in a mixed-criticality scheduling framework motivated by the needs of next-generation unmanned air vehicles.

[1]  Shinpei Kato,et al.  Gang EDF Scheduling of Parallel Task Systems , 2009, 2009 30th IEEE Real-Time Systems Symposium.

[2]  Marco Caccamo,et al.  Memory-centric scheduling for multicore hard real-time systems , 2012, Real-Time Systems.

[3]  Edward A. Lee,et al.  PRET DRAM controller: Bank privatization for predictability and temporal isolation , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[4]  Lui Sha,et al.  Impact of Cache Partitioning on Multi-tasking Real Time Embedded Systems , 2008, 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications.

[5]  Damien Hardy,et al.  Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches , 2009, 2009 30th IEEE Real-Time Systems Symposium.

[6]  James H. Anderson,et al.  Soft real-time scheduling on multiprocessors , 2006 .

[7]  Jochen Liedtke,et al.  OS-controlled cache predictability for real-time systems , 1997, Proceedings Third IEEE Real-Time Technology and Applications Symposium.

[8]  Sanjoy K. Baruah,et al.  Mixed-Criticality Real-Time Scheduling for Multicore Systems , 2010, 2010 10th IEEE International Conference on Computer and Information Technology.

[9]  Francisco J. Cazorla,et al.  IA^3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems , 2011, 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium.

[10]  A. Marti Campoy,et al.  DYNAMIC USE OF LOCKING CACHES IN MULTITASK, PREEMPTIVE REAL-TIME SYSTEMS , 2002 .

[11]  James H. Anderson,et al.  RTOS Support for Multicore Mixed-Criticality Systems , 2012, 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium.

[12]  Kees G. W. Goossens,et al.  Predator: A predictable SDRAM memory controller , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[13]  Francisco J. Cazorla,et al.  Hardware support for WCET analysis of hard real-time multicore systems , 2009, ISCA '09.

[14]  Nuno Pereira,et al.  Static-Priority Scheduling over Wireless Networks with Multiple Broadcast Domains , 2007, RTSS 2007.

[15]  James H. Anderson,et al.  Supporting Nested Locking in Multiprocessor Real-Time Systems , 2012, 2012 24th Euromicro Conference on Real-Time Systems.

[16]  Michael Paulitsch,et al.  Leveraging Multi-core Computing Architectures in Avionics , 2012, 2012 Ninth European Dependable Computing Conference.

[17]  M. Campoy,et al.  Static Use of Locking Caches in Multitask Preemptive Real-Time Systems , 2001 .

[18]  Frank Mueller,et al.  Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks , 2006, 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06).

[19]  Francisco J. Cazorla,et al.  Assessing the suitability of the NGMP multi-core processor in the space domain , 2012, EMSOFT '12.

[20]  PaolieriMarco,et al.  Hardware support for WCET analysis of hard real-time multicore systems , 2009 .

[21]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[22]  Wang Yi,et al.  Outstanding Paper Award: Bounding and Shaping the Demand of Mixed-Criticality Sporadic Tasks , 2012, 2012 24th Euromicro Conference on Real-Time Systems.

[23]  Chung-Lun Li,et al.  Scheduling with processing set restrictions: A survey , 2008 .

[24]  Sanjoy K. Baruah,et al.  Towards the Design of Certifiable Mixed-criticality Systems , 2010, 2010 16th IEEE Real-Time and Embedded Technology and Applications Symposium.

[25]  James H. Anderson,et al.  Scheduling and locking in multiprocessor real-time operating systems , 2011 .

[26]  Marco Caccamo,et al.  A Predictable Execution Model for COTS-Based Embedded Systems , 2011, 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium.

[27]  Bryan C. Ward,et al.  Nested Multiprocessor Real-Time Locking with Improved Blocking ∗ , 2012 .

[28]  Frank Mueller Compiler support for software-based cache partitioning , 1995 .

[29]  Damien Hardy,et al.  WCET Analysis of Multi-Level Set-Associative Data Caches , 2009, WCET.

[30]  Kees G. W. Goossens,et al.  A TDM NoC supporting QoS, multicast, and fast connection set-up , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[31]  Sanjoy K. Baruah,et al.  The Preemptive Uniprocessor Scheduling of Mixed-Criticality Implicit-Deadline Sporadic Task Systems , 2012, 2012 24th Euromicro Conference on Real-Time Systems.

[32]  Frank Mueller,et al.  Compiler support for software-based cache partitioning , 1995, Workshop on Languages, Compilers, & Tools for Real-Time Systems.

[33]  Steve Vestal,et al.  Preemptive Scheduling of Multi-criticality Systems with Varying Degrees of Execution Time Assurance , 2007, 28th IEEE International Real-Time Systems Symposium (RTSS 2007).

[34]  D. B. Kirk,et al.  SMART (strategic memory allocation for real-time) cache design , 1989, [1989] Proceedings. Real-Time Systems Symposium.