VLSI methodology for the design of RNS and QRNS full adder based converters

A unified graph-based methodology for designing VLSI residue number system (RNS) converters from binary system to RNS to quadratic RNS (QRNS) and conversely, using full adders (FAs) as the basic building block, is introduced. The design procedure produces array architectures starting from the algorithm bit level description of each converter and ending up with the hardware implementation, through a number of steps. These steps specify in a systematic way the minimum number of FAs for performing a conversion, as well as the interconnections among the FAs. They are implemented into a two-dimensional regular array processor and characterised by small hardware and area-time complexity, and high throughput rate, compared with existing implementations. The derived architectures are generalised, covering a wide range of moduli and input bits.

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