论文信息 - Systolic Modular Multiplication

Systolic Modular Multiplication

A systolic array for modular multiplication is presented using the ideally suited algorithm of P.L. Montgomery (1985). Throughput is one modular multiplication every clock cycle, with a latency of 2n+2 cycles for multiplicands having n digits. Its main use would be where many consecutive multiplications are done, as in RSA cryptosystems. >

C. D. Walter | Colin D. Walter

[1] Adi Shamir,et al. A method for obtaining digital signatures and public-key cryptosystems , 1978, CACM.

[2] John V. McCanny,et al. Implementation of signal processing functions using 1-bit systolic arrays , 1982 .

[3] Ching Yu Hung,et al. Bit-level systolic arrays for modular multiplication , 1991, J. VLSI Signal Process..

[4] Colin D. Walter,et al. Hardware Implementation of Montgomery's Modular Multiplication Algorithm , 1993, IEEE Trans. Computers.

[5] P. L. Montgomery. Modular multiplication without trial division , 1985 .

[6] Mark Shand,et al. Hardware speedups in long integer multiplication , 1991, SIGARCH Comput. Archit. News.

[7] Ernest F. Brickell,et al. A Fast Modular Multiplication Algorithm With Application To Two Key Cryptography , 1982, CRYPTO.

[8] Stephen E. Eldridge. A faster modular multiplication algorithm , 1991, Int. J. Comput. Math..