Exploiting multicycle false paths in the performance optimization of sequential logic circuits

This paper addresses the performance optimization problem for sequential logic circuits. It is shown how the notion of false paths, traditionally defined for combinational logic circuits, can be extended to the sequential context by considering the operation of the circuit over multiple clock-cycles. These multicycle false paths can be removed from the circuit using techniques similar to those proposed for combinational logic circuits. This observation offers new techniques to improve the performance of sequential logic circuits. An implementation of an algorithm that uses these ideas shows significant performance improvement on some typical benchmark circuits at a modest area overhead. >

[1]  Masahiro Fujita,et al.  Efficient sum-to-one subsets algorithm for logic optimization , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[2]  Sharad Malik,et al.  Delay computation in combinational logic circuits: theory and algorithms , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[3]  David Hung-Chang Du,et al.  Path sensitization in critical path problem , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[4]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[5]  Giovanni De Micheli,et al.  Synchronous logic synthesis: algorithms for cycle-time minimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Robert K. Brayton,et al.  Sequential circuit design using synthesis and optimization , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[7]  Robert K. Brayton,et al.  Performance-oriented technology mapping , 1990 .

[8]  Robert K. Brayton,et al.  Timing optimization of combinational logic , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[9]  Robert K. Brayton,et al.  Computing the initial states of retimed circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Robert K. Brayton,et al.  Circuit structure relations to redundancy and delay: the KMS algorithm revisited , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[11]  Robert K. Brayton,et al.  Integrating functional and temporal domains in logic design , 1991 .

[12]  Robert K. Brayton,et al.  Implicit state enumeration of finite state machines using BDD's , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[13]  Robert K. Brayton,et al.  Retiming and resynthesis: optimizing sequential networks with combinational techniques , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Masahiro Fujita,et al.  Network Resynthesis Algorithms for Delay Minimization (Special Issue on Synthesis and Verification of Hardware Design) , 1993 .

[15]  Srinivas Devadas,et al.  Test generation for highly sequential circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[16]  Alexander Saldanha,et al.  Is redundancy necessary to reduce delay? , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Robert K. Brayton,et al.  Performance optimization of pipelined circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[18]  David Hung-Chang Du,et al.  Path sensitization in critical path problem [logic circuit design] , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..