Implementation of High Speed and Low Area Extended Euclidean Inversion over Ternary Fields
暂无分享,去创建一个
[1] Fayez Gebali,et al. Systolic design space exploration of polynomial division over GF(m2) , 2017, 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE).
[2] Ç. Koç,et al. A Novel and Efficient Processor for ECC over GF (3) and its FPGA Implementation , 2009 .
[3] Paulo S. L. M. Barreto,et al. Efficient Hardware for the Tate Pairing Calculation in Characteristic Three , 2005, CHES.
[4] Hsie-Chia Chang,et al. Efficient Hardware Architecture of $\eta_{T}$ Pairing Accelerator Over Characteristic Three , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[5] Andreas Curiger,et al. On Computing Multiplicative Inverses in GF(2^m) , 1993, IEEE Trans. Computers.
[6] Tsuyoshi Takagi,et al. Faster Implementation of eta-T Pairing over GF(3m) Using Minimum Number of Logical Instructions for GF(3)-Addition , 2008, Pairing.
[7] Alfred Menezes,et al. Software Implementation of Arithmetic in F3m , 2007, WAIFI.
[8] Fayez Gebali,et al. Systolic Design Space Exploration of Polynomial Division over $$GF(3^m)$$ , 2018 .
[9] Fayez Gebali,et al. Algorithms and Parallel Computing , 2011 .
[10] Nigel P. Smart,et al. Software Implementation of Finite Fields of Characteristic Three, for Use in Pairing-based Cryptosystems , 2002 .
[11] Tim Kerins,et al. Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes , 2004, FPL.
[12] Fayez Gebali,et al. New systolic array architecture for finite field division , 2018, IEICE Electron. Express.
[13] Fayez Gebali,et al. New Systolic Array Architecture for Finite Field Inversion , 2017, Canadian Journal of Electrical and Computer Engineering.
[14] Sedat Akleylek,et al. On the arithmetic operations over finite fields of characteristic three with low complexity , 2014, J. Comput. Appl. Math..
[15] Reza Azarderakhsh,et al. Post-Quantum Cryptography on FPGA Based on Isogenies on Elliptic Curves , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.
[16] Tim Kerins,et al. A Reconfigurable Processor for the Cryptographic ηT Pairing in Characteristic 3 , 2007, Fourth International Conference on Information Technology (ITNG'07).
[17] Joos Vandewalle,et al. Hardware architectures for public key cryptography , 2003, Integr..