A new processor interconnection structure for fault tolerant processor arrays

Processor arrays integrated on a wafer can display a high performance mainly due to the short communication delay between processors. However, an efficient fault tolerance scheme is essential to yield the desired array because some components on wafer can be defective. In this paper, the authors present a new processor interconnection structure which requires much less chip area than the traditional design for restructuring a rectangular array. Because interconnection of a fault tolerant processor array occupies a substantial chip area, especially for large word parallel systems, this will significantly improve the overall performance of the processor arrays in VLSI/WSI.<<ETX>>