Optimized Reversible Montgomery Multiplier

Reversible computation is of the growing interests to power minimization which has applications in low power CMOS design, quantum computing, optical information processing, DNA computing, bioinformatics and nanotechnology. The major component of any computing device is ALU. In order to design the reversible ALU of a crypto-processor, a high speed multiplier such as Montgomery multiplier is used. This multiplier requires efficient sequential circuits such as reversible registers, shift registers and reversible carry save adder (CSA). In this paper four to two CSA is designed using proposed reversible FAG gate and reversible sequential circuits are designed using reversible DFG gate. This will provide a starting point for developing cryptosystems secured against DPA attacks. This paper presents a better design when compared with the existing ones in terms of number of gates and number of garbage outputs. KeywordsALU; Carry save adder; Montgomery multiplier; Reversible D flip flop; Shift register.

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