A memory grouping method for sharing memory BIST logic

With the increasing demand for SoCs to include rich functionality, SoCs are being designed with hundreds of small memories with different sizes and frequencies. If memory BIST logics were individually added to these various memories, the area overhead would be very high. To reduce the overhead, memory BIST logic must therefore be shared. This paper proposes a memory-grouping method for memory BIST logic sharing. A memory-grouping problem is formulated and an algorithm to solve the problem is proposed. Experimental results showed that the proposed method reduced the area of the memory BIST wrapper by up to 40.55%. The results also showed that the ability to select from two types of connection methods produced a greater reduction in area than using a single connection method

[1]  Charles E. Stroud A Designer's Guide to Built-In Self-Test , 2002 .

[2]  Nilanjan Mukherjee,et al.  Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm , 2002, Proceedings. International Test Conference.

[3]  Erik Jan Marinissen,et al.  On using rectangle packing for SOC wrapper/TAM co-optimization , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[4]  Alfredo Benso,et al.  A programmable BIST architecture for clusters of multiple-port SRAMs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[5]  Toshihide Ibaraki,et al.  Computing Edge-Connectivity in Multigraphs and Capacitated Graphs , 1992, SIAM J. Discret. Math..