A 200 V silicon-on-sapphire LDMOS structure with a step oxide extended field plate

Abstract Fabrication of power integrated circuits on silicon-on-sapphire (SOS) substrates has rarely been considered before. Hence, there is a lack of research in lateral power devices integrated on SOS. Self-heating effects in existing silicon-on-insulator (SOI) lateral power devices degrade the device performance and their reliability. Use of SOS substrates could alleviate these problems though they would require a different approach in lateral power device engineering. This paper purposes a new power SOS LDMOS structure with reduced transient self-heating effects and enhanced current capability compared to the conventional SOI counterpart. The proposed lateral power structure integrated on SOS substrates is analyzed by electro-thermal simulations. The field plate is enlarged (extended field plate (EFP)) along the drift region, reaching the drain region. The EFP includes an oxide step which improves the “on-state resistance–breakdown voltage” trade-off (RONxS–Vbr).

[1]  T. Fujihira,et al.  Simulated superior performances of semiconductor superjunction devices , 1998, Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No.98CH36212).

[2]  R. Constapel,et al.  Thermal behaviour of lateral power devices on SOI substrates , 1994, Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics.

[3]  Breakdown voltage improvement for thin-film SOI power MOSFET's by a buried oxide step structure , 1994, IEEE Electron Device Letters.

[4]  M. Vellvehi,et al.  Radial confinement in lateral power devices , 2001 .

[5]  Bantval J. Baliga,et al.  Extension of RESURF principle to dielectrically isolated power devices , 1991, [1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs.

[6]  B Barnwell,et al.  SUDAAN User's Manual, Release 7.5, , 1997 .

[7]  A. Heringa,et al.  Extended (180 V) voltage in 0.6 /spl mu/m thin-layer-SOI A-BCD3 technology on 1 /spl mu/m BOX for display, automotive and consumer applications , 2002, Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.

[8]  C.A.T. Salama,et al.  Super junction LDMOST in silicon-on-sapphire technology (SJ-LDMOST) , 2002, Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.

[9]  H. Pein,et al.  Comparison of self-heating effects in bulk-silicon and SOI high-voltage devices , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[10]  Florin Udrea,et al.  Minority carrier injection across the 3D RESURF junction , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).

[11]  T. Letavic,et al.  High performance 600 V smart power technology based on thin layer silicon-on-insulator , 1997, Proceedings of 9th International Symposium on Power Semiconductor Devices and IC's.

[12]  Il-Jung Kim,et al.  Analytical approach to breakdown voltages in thin-film SOI power MOSFETs , 1996 .

[13]  Sorin Cristoloveanu,et al.  Electrical evaluation of innovating processes for improving SOS materials , 2001 .

[14]  Young-Se Kwon,et al.  Graded etching of thermal oxide with various angles using silicafilm , 1980 .

[15]  P. M. Asbeck,et al.  Advanced thin-film silicon-on-sapphire technology: microwave circuit applications , 1998 .

[16]  M. Burgener,et al.  High-quality CMOS in thin (100 nm) silicon on sapphire , 1988, IEEE Electron Device Letters.