This paper shows how to generate a finite-vertex graph, called a reachability graph for discrete event system specification (DEVS) network. The reachability graph is isomorphic to a given original DEVS network in terms of behavior but the number of vertices as well as the number of edges of the reachability graph are finite. To obtain the finite-vertex reachability graph of a DEVS network, this paper uses a subclass of DEVS, called finite and deterministic DEVS (FD-DEVS). This subclass has been restricted to have (1) finite sets of both events and states, (2) the rational-number time advance function, (3) time independent external transition, and (4) selective reschedule functionality. For abstracting the infinite-state behavior of DEVS network, we use the concept of time zone, invented by Dill [3], that is a conjunction of inequalities of elapsed times. Based-on time zone abstraction, an algorithm for generating the reachability graph of a DEVS network is proposed and its completeness and complexity are addressed. Questions concerning qualitative properties, for examples, “Does this DEVS network have any possibility to reach a bad situation?” or “Will this system repeat a certain pattern forever?” are open problems for more than 30 years. This paper gives an answer about the above questions for the FD-DEVS subclass of DEVS. A reachability graph-based qualitative verification is exemplified with a modular monorail system, so the reader will find the usefulness of the reachability graph. Note to Practitioners— Modular and hierarchical modeling and analysis becomes more important as systems are increasingly complicated [10]. DEVS formalism is a modular and hierarchical formalism in which the user build a system by connecting system components, and the system can be a component in a bigger system. In addition, the practitioners can use the all source codes of the algorithm and the verification example proposed in this paper which are available at http://xsycsharp.sourceforge.net/DEVSsharp.
[1]
Bernard P. Zeigler,et al.
Processing Time Bounds of Schedule-Preserving DEVS ⁄
,
2007
.
[2]
M. W. Shields.
An Introduction to Automata Theory
,
1988
.
[3]
Robert Sedgewick,et al.
Algorithms in C : Part 5 : Graph Algo-rithms
,
2002
.
[4]
David L. Dill,et al.
Timing Assumptions and Verification of Finite-State Concurrent Systems
,
1989,
Automatic Verification Methods for Finite State Systems.
[5]
Robert Sedgewick,et al.
Algorithms in C
,
1990
.
[6]
David R.C. Hill.
Theory of Modelling and Simulation: Integrating Discrete Event and Continuous Complex Dynamic Systems
,
2000
.
[7]
Bernard P. Zeigler,et al.
Hierarchical modeling for discrete event simulation (panel)
,
1993,
WSC '93.
[8]
Bernard P. Zeigler,et al.
Symbolic discrete event system specification
,
1991,
[1991] Proceedings. The Second Annual Conference on AI, Simulation and Planning in High Autonomy Systems.
[9]
Tag Gon Kim,et al.
Application of Real-Time DEVS to Analysis of Safety-Critical Embedded Control Systems: Railroad Crossing Control Example
,
2005,
Simul..
[10]
Bernard P. Zeigler,et al.
Theory of Modelling and Simulation
,
1979,
IEEE Transactions on Systems, Man, and Cybernetics.
[11]
Stephan Merz,et al.
Model Checking
,
2000
.
[12]
Bernard P. Zeigler,et al.
Expressiveness of verifiable hierarchical clock systems
,
2008,
Int. J. Gen. Syst..
[13]
Moon Ho Hwang.
Generating finite-state global behavior of reconfigurable automation systems: DEVS approach
,
2005,
IEEE International Conference on Automation Science and Engineering, 2005..
[14]
Jeffrey D. Ullman,et al.
Introduction to Automata Theory, Languages and Computation
,
1979
.
[15]
Tag Gon Kim,et al.
Timed I/O Test Sequences for Discrete Event Model Verification
,
2004,
AIS.