论文信息 - AMD SOC power management: Improving performance/watt using run-time feedback

AMD SOC power management: Improving performance/watt using run-time feedback

This paper presents an analysis of four runtime power management features implemented in AMD's recent 28nM APU. These features optimize SOC performance by shifting power and frequency resources in response to workload characteristics. The Global Efficient APM (GEAPM), Core-Bound Boost (CBB) and Memory-Bound Boost (MBB) features are shown to provide a performance improvement of up to 76%, 4.3% and 12.5% respectively. The Local Efficient APM (LEAPM) feature is shown to reduce average CPU power consumption by 34% while reducing performance by less than 1%.

William Lloyd Bircher | Samuel Naffziger | S. Naffziger | W. Bircher

[1] Alon Naveh,et al. Power management architecture of the 2nd generation Intel® Core microarchitecture, formerly codenamed Sandy Bridge , 2011, IEEE Hot Chips Symposium.

[2] Sudhakar Yalamanchili,et al. Cooperative boosting: needy versus greedy power management , 2013, ISCA.

[3] Margaret Martonosi,et al. Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data , 2003, MICRO.

[4] Efraim Rotem,et al. Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy Bridge , 2012, IEEE Micro.

[5] Lloyd Bircher,et al. Richland client APU , 2013, 2013 IEEE Hot Chips 25 Symposium (HCS).

[6] Wu-chun Feng,et al. Effective Dynamic Voltage Scaling Through CPU-Boundedness Detection , 2004, PACS.

[7] Maurice Steinman,et al. AMD Fusion APU: Llano , 2012, IEEE Micro.