A survey on design of digital signal processor

This present paper deals with the exhaustive review of literature based on different algorithms for design of high speed digital signal processor. To make an efficient and effective processor the features like pipelining, parallelism and hazard handling capabilities are used. High speed multipliers, divider and adders are prime requirement for DSP operations. The multiplier has been designed using Urdhva triyakbhyam algorithm and binary division can be implemented using NND and Paravartya method. It requires less time, power and gives results faster.

[1]  R. M. Banakar,et al.  High speed signed multiplier for Digital Signal Processing applications , 2012, 2012 IEEE International Conference on Signal Processing, Computing and Control.

[2]  Rajesh Mahle,et al.  Design a DSP operations using vedic mathematics , 2013, 2013 International Conference on Communication and Signal Processing.

[3]  Abhyarthana Bisoyi,et al.  Comparison of a 32-bit Vedic multiplier with a conventional binary multiplier , 2014, 2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies.

[5]  Chan Mo Kim,et al.  Multiplier design based on ancient Indian Vedic Mathematics , 2008, 2008 International SoC Design Conference.

[6]  Vaijyanath Kunchigi,et al.  32-BIT MAC UNIT DESIGN USING VEDIC MULTIPLIER , 2013 .

[7]  Ashutosh Gupta,et al.  Energy efficient and high performance 64-bit Arithmetic Logic Unit using 28nm technology , 2015, 2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI).

[8]  Jusung Park,et al.  Design and implementation of 16-bit fixed point digital signal processor , 2008, 2008 International SoC Design Conference.

[10]  Zhiying Wang,et al.  Design of a Configurable Embedded Processor Architecture for DSP Functions , 2005, 11th International Conference on Parallel and Distributed Systems (ICPADS'05).

[11]  E. O'Malley,et al.  A 16-bit fixed-point digital signal processor for digital power converter control , 2005, Twentieth Annual IEEE Applied Power Electronics Conference and Exposition, 2005. APEC 2005..

[12]  M. Nagaraju,et al.  High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics , 2013 .

[13]  Johann Großschädl,et al.  A single-cycle (32/spl times/32+32+64)-bit multiply/accumulate unit for digital signal processing and public-key cryptography , 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

[14]  Tasnim Ferdous.  Design and FPGA-based implementation of a high performance 32-bit DSP processor , 2012, 2012 15th International Conference on Computer and Information Technology (ICCIT).

[15]  A. Dandapat,et al.  High speed ASIC design of complex multiplier using Vedic Mathematics , 2011, IEEE Technology Students' Symposium.