A 2.4 GS/s, 4.9 ENOB at Nyquist, single-channel pipeline ADC in 65nm CMOS

This paper presents a high-speed single channel pipeline analog-to-digital converter sampling at 2.4 GS/s which, to the authors' best knowledge, is the fastest reported for pipeline converters. The use of a time-borrowing clocking scheme eliminates the comparator latency from the critical path and together with the use of fast open-loop current-mode amplifiers the high sample rate is achieved. Implemented in a 65nm general purpose CMOS technology the effective number of bits is above 4.7 in the Nyquist band, being 5.4 and 4.9 at DC and Nyquist respectively. This shows that very fast pipeline ADCs are possible to implement as key building blocks in interleaved structures.

[1]  Ding-Lan Shen,et al.  A 6-Bit 800-MS/s Pipelined A/D Converter with Open-Loop Amplifiers , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[2]  A. Varzaghani,et al.  A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization , 2009, IEEE Journal of Solid-State Circuits.

[3]  S. Ramprasad,et al.  A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS , 2008, 2008 IEEE Symposium on VLSI Circuits.

[4]  Boris Murmann,et al.  Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  B. Razavi,et al.  A 10-Bit 500-MS/s 55-mW CMOS ADC , 2009, IEEE Journal of Solid-State Circuits.