Optimization of Latency Insensitive Systems Through Back Pressure Minimization
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Sandeep K. Shukla | S. S. Ravi | Bin Xue | S. Ravi | S. Shukla | Bin Xue
[1] Josep Carmona,et al. Elastic Circuits , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] Josep Carmona,et al. Scheduling Synchronous Elastic Designs , 2009, 2009 Ninth International Conference on Application of Concurrency to System Design.
[3] Yvon Savaria,et al. Optimal design of synchronous circuits using software pipelining techniques , 2001, TODE.
[4] Fritz Bock. An algorithm to construct a minimum directed spanning tree in a directed network , 1971 .
[5] Luca P. Carloni. The Role of Back-Pressure in Implementing Latency-Insensitive Systems , 2006, Electron. Notes Theor. Comput. Sci..
[6] Alberto L. Sangiovanni-Vincentelli,et al. Theory of latency-insensitive design , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] Karsten Schmidt. LoLA: a low level analyser , 2000 .
[8] Luca P. Carloni,et al. Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Jordi Cortadella,et al. Performance optimization of elastic systems using buffer resizing and buffer insertion , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.
[10] Sandeep K. Shukla,et al. Analysis of Scheduled Latency Insensitive Systems with Periodic Clock Calculus , 2010 .
[11] Pradip Bose,et al. Synchronous interlocked pipelines , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.
[12] Jordi Cortadella,et al. Synchronous Elastic Circuits with Early Evaluation and Token Counterflow , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[13] Julien Boucaron,et al. Formal Methods for Scheduling of Latency-Insensitive Designs , 2007, EURASIP J. Embed. Syst..
[14] Charles E. Leiserson,et al. Retiming synchronous circuitry , 1988, Algorithmica.
[15] Steven M. Nowick,et al. Robust interfaces for mixed-timing systems , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[16] Yang Xu,et al. Performance Evaluation of Elastic GALS Interfaces and Network Fabric , 2008, Electron. Notes Theor. Comput. Sci..
[17] Jordi Cortadella,et al. Synthesis of synchronous elastic architectures , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[18] Robert E. Tarjan,et al. Finding optimum branchings , 1977, Networks.
[19] Sandeep K. Shukla,et al. Minimizing back pressure for latency insensitive system synthesis , 2010, Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010).
[20] Luca P. Carloni,et al. Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[21] Cheng-Kok Koh,et al. Performance optimization of latency insensitive systems through buffer queue sizing of communication channels , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).
[22] Mario R. Casu,et al. Adaptive Latency-Insensitive Protocols , 2007, IEEE Design & Test of Computers.
[23] Rajesh K. Gupta,et al. Faster maximum and minimum mean cycle algorithms for system-performance analysis , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[24] Robert E. Tarjan,et al. Depth-First Search and Linear Graph Algorithms , 1972, SIAM J. Comput..
[25] Éva Tardos,et al. Algorithm design , 2005 .
[26] Cheng-Kok Koh,et al. Performance analysis of latency-insensitive systems , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[27] Sandeep K. Shukla,et al. Optimization of back pressure and throughput for latency insensitive systems , 2010, 2010 IEEE International Conference on Computer Design.
[28] Alberto L. Sangiovanni-Vincentelli,et al. Combining retiming and recycling to optimize the performance of synchronous circuits , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..
[29] Mario R. Casu,et al. A new approach to latency insensitive design , 2004, Proceedings. 41st Design Automation Conference, 2004..
[30] Tadao Murata,et al. Petri nets: Properties, analysis and applications , 1989, Proc. IEEE.
[31] Jordi Cortadella,et al. Performance optimization of elastic systems using buffer resizing and buffer insertion , 2008, ICCAD 2008.