Global Routing With Timing Constraints

We show how to incorporate global static timing constraints into global routing. Our approach is based on the min–max resource sharing model that proved successful for global routing in theory and practice. Static timing constraints are modeled by a linear number of additional resources and customers. The algorithm dynamically adjusts delay budgets and can, thus, tradeoff wiring congestion for delay. As a subroutine, the algorithm routes a single net. If this subroutine is near-optimal, we will find near-optimal solutions for the overall problem very efficiently. The approach works for many delay models; here we discuss a linear delay model (before buffering) and the Elmore delay model (after buffering). We demonstrate the benefit of our timing-constrained global routing algorithm by experimental results on industrial chips.

[1]  Sachin S. Sapatnekar,et al.  A timing-constrained simultaneous global routing algorithm , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Satish Rao,et al.  Approximating geometrical graphs via “spanners” and “banyans” , 1998, STOC '98.

[3]  Dirk Müller,et al.  Algorithms and data structures for fast and good VLSI routing , 2013, DAC Design Automation Conference 2012.

[4]  Andrew B. Kahng,et al.  Floorplan evaluation with timing-driven global wireplanning, pin assignment, and buffer/wire sizing , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[5]  Satoshi Goto,et al.  Delay-driven layer assignment in global routing under multi-tier interconnect structure , 2013, ISPD '13.

[6]  Adil I. Erzin,et al.  A provably tight delay-driven concurrently congestion mitigating global routing algorithm , 2015, Appl. Math. Comput..

[7]  Joseph Naor,et al.  On the approximability of some network design problems , 2005, SODA '05.

[8]  Rudolf Scheifele RC-aware global routing , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[9]  C. L. Liu,et al.  Optimization of the maximum delay of global interconnects duringlayer assignment , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Kamesh Munagala,et al.  Cost-distance: two metric network design , 2000, Proceedings 41st Annual Symposium on Foundations of Computer Science.

[11]  Marcus Brazil,et al.  Optimal Interconnection Trees in the Plane: Theory, Algorithms and Applications , 2015 .

[12]  Jens Vygen Near-Optimum Global Routing with Coupling, Delay Bounds, and Power Consumption , 2004, IPCO.

[13]  Malgorzata Marek-Sadowska,et al.  Minimal Delay Interconnect Design Using Alphabetic Trees , 1994, 31st Design Automation Conference.

[14]  Jens Vygen,et al.  Approximation algorithms for a facility location problem with service capacities , 2008, TALG.

[15]  W. C. Elmore The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[16]  Mark Horowitz,et al.  Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Samir Khuller,et al.  Balancing minimum spanning and shortest path trees , 1993, SODA '93.

[18]  Jens Vygen,et al.  Dijkstra meets Steiner: a fast exact goal-oriented Steiner tree algorithm , 2017, Math. Program. Comput..

[19]  Jens Vygen,et al.  Efficient generation of short and fast repeater tree topologies , 2006, ISPD '06.

[20]  Rudolf Scheifele Steiner Trees with Bounded RC-Delay , 2014, WAOA.

[21]  David S. Johnson,et al.  The Rectilinear Steiner Tree Problem is NP Complete , 1977, SIAM Journal of Applied Mathematics.

[22]  Stephan Held,et al.  Shallow-Light Steiner Arborescences with Vertex Delays , 2013, IPCO.

[23]  Ting-Chi Wang,et al.  An enhanced global router with consideration of general layer directives , 2011, ISPD '11.

[24]  Andrew B. Kahng,et al.  Rectilinear Steiner Trees with Minimum Elmore Delay , 1994, 31st Design Automation Conference.

[25]  Jin-Tai Yan,et al.  Multilevel timing-constrained full-chip routing in hierarchical quad-grid model , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[26]  Eugene Shragowitz,et al.  A global router based on a multicommodity flow model , 1987, Integr..

[27]  Lawrence T. Pileggi,et al.  RICE: rapid interconnect circuit evaluation using AWE , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[28]  Sanjeev Arora,et al.  Polynomial time approximation schemes for Euclidean traveling salesman and other geometric problems , 1998, JACM.

[29]  Xianlong Hong,et al.  TIGER: an efficient timing-driven global router for gate array and standard cell layout design , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  Martin Zachariasen,et al.  Delay-related secondary objectives for rectilinear Steiner minimum trees , 2004, Discret. Appl. Math..

[31]  Cliff C. N. Sze,et al.  Wire synthesizable global routing for timing closure , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[32]  Jin-Tai Yan,et al.  Liming-constrained congestion-driven global routing , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[33]  A. Kahng,et al.  On optimal interconnections for VLSI , 1994 .

[34]  Andrew B. Kahng,et al.  High-Performance Routing Trees with Identified Critical Sinks , 1993, 30th ACM/IEEE Design Automation Conference.

[35]  Dirk Müller,et al.  Global routing with inherent static timing constraints , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[36]  F. Hwang On Steiner Minimal Trees with Rectilinear Distance , 1976 .

[37]  Shiyan Hu,et al.  A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[38]  Andrew B. Kahng,et al.  Near-optimal critical sink routing tree constructions , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[39]  Dirk Müller,et al.  Optimizing yield in global routing , 2006, ICCAD '06.

[40]  Shiyan Hu,et al.  CATALYST: Planning layer directives for effective design closure , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[41]  Dirk Müller,et al.  Faster min–max resource sharing in theory and practice , 2011, Math. Program. Comput..

[42]  Xianlong Hong,et al.  An Efficient Timing-Driven Global Routing Algorithm , 1993, 30th ACM/IEEE Design Automation Conference.

[43]  Prabhakar Raghavan,et al.  Randomized rounding: A technique for provably good algorithms and algorithmic proofs , 1985, Comb..