Generalized Power-Delay Metrics in Deep Submicron CMOS Designs

Recently, designers have been using the energy-delay product as a metric of goodness for CMOS designs due to certain perceived shortcomings of the more traditional power-delay product. As the industry moves to 90-nm technology with higher leakage currents, it is appropriate to revisit existing design metrics. In this paper, a reevaluation of the metrics is carried out, and a generalized set of metrics is proposed. Supply voltage (VDD) and threshold voltage (VT) scaling are two popular approaches to power reduction. As such, the effects on power and frequency are analyzed, and the feasible region of operation is identified in the VDD versus VT plane. A fundamental relationship is established between the optimal operating points and the generalized design metrics. The initial findings also indicate that some designs may have a higher percentage of leakage than expected to achieve overall power reduction, running somewhat counter to conventional wisdom

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