Speculative execution exception recovery using write-back suppression
暂无分享,去创建一个
[1] Gurindar S. Sohi,et al. Instruction Issue Logic for High-Performance Interruptible, Multiple Functional Unit, Pipelines Computers , 1990, IEEE Trans. Computers.
[2] Soo-Mook Moon,et al. Increasing Instruct ion-level Parallelism through Multi-way Branching , 1993, 1993 International Conference on Parallel Processing - ICPP'93.
[3] Michael D. Smith,et al. Boosting beyond static scheduling in a superscalar processor , 1990, ISCA '90.
[4] Soo-Mook Moon,et al. On Performance and Efficiency of VLIW and Superscalar , 1993, 1993 International Conference on Parallel Processing - ICPP'93.
[5] Yale N. Patt,et al. Critical issues regarding HPS, a high performance microarchitecture , 1985, MICRO 18.
[6] Soo-Mook Moon,et al. Selective Scheduling Framework for Speculative Operations in VLIW and Superscalar Processors , 1993, Architectures and Compilation Techniques for Fine and Medium Grain Parallelism.
[7] Joseph A. Fisher,et al. Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.
[8] Gurindar S. Sohi,et al. High-bandwidth data memory systems for superscalar processors , 1991, ASPLOS IV.
[9] Soo-Mook Moon,et al. Hardware implementation of a general multi-way jump mechanism , 1990, [1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture.
[10] Toshio Nakatani,et al. “Combining” as a compilation technique for VLIW architectures , 1989, MICRO 22.
[11] Kemal Ebcioglu,et al. An efficient resource-constrained global scheduling technique for superscalar and VLIW processors , 1992, MICRO 1992.
[12] Scott A. Mahlke,et al. Sentinel scheduling for VLIW and superscalar processors , 1992, ASPLOS V.
[13] Kemal Ebcioglu,et al. An architectural framework for migration from CISC to higher performance platforms , 1992, ICS '92.
[14] Scott A. Mahlke,et al. IMPACT: an architectural framework for multiple-instruction-issue processors , 1991, ISCA '91.
[15] Anne Rogers,et al. Software support for speculative loads , 1992, ASPLOS V.
[16] Michael D. Smith,et al. Limits on multiple instruction issue , 1989, ASPLOS 1989.
[17] David W. Wall,et al. Limits of instruction-level parallelism , 1991, ASPLOS IV.
[18] Michael D. Smith,et al. Efficient superscalar performance through boosting , 1992, ASPLOS V.
[19] Scott Mahlke,et al. Sentinel scheduling: a model for compiler-controlled speculative execution , 1993 .
[20] Michael Rodeh,et al. Global instruction scheduling for superscalar machines , 1991, PLDI '91.
[21] Alexander Aiken,et al. A Development Environment for Horizontal Microcode , 1986, IEEE Trans. Software Eng..
[22] Edward M. Riseman,et al. The Inhibition of Potential Parallelism by Conditional Jumps , 1972, IEEE Transactions on Computers.