Isolation of nanowires made on bulk wafers by ground plane doping

In this work, the electrical isolation of nanowires fabricated on bulk wafers is investigated. It is shown that electrical isolation can be realized with a Ground Plane isolation implant at the beginning of the process flow. For transistors using extensions, it is seen that a relatively high dose of Ground Plane doping is needed in order to avoid punchthrough through a parasitic channel less controlled by the gate (compared to the nanowires electrostatic control). However, the minimum reachable off state leakage current IOFF is also increased for higher Ground plane doping due to junction leakage increase, and may impose a device trade-off between the reachable IOFF target and the short channel effects control. In order to alleviate this issue, it is proposed to skip extensions in order to reduce the dependence of short channel effects to Ground Plane doping dose. Experimental NMOS and PMOS extensionless nanowires are demonstrated without ground plane doping, and feature no ION/short channel control penalty compared to reference transistors (using extensions).