An Introduction to Switch-Level Modeling

Switch-level modeling is a recently developed design and analysis methodology for MOS VLSI circuits. At the switch level, important features of MOS circuits can be directly modeled using a moderate number of discrete parameters, including switch states, resistance, capacitance, and bidirectional signals. Switch-level models, provide more accurate behavioral and structural information than gate-level logical models, while avoiding the high computational cost associated with analog electrical models.

[1]  John P. Hayes Fault Modeling for Digital MOS Integrated Circuits , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Eduard Cerny,et al.  Simulation of MOS Circuits by Decision Diagrams , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Basant R. Chawla,et al.  Motis - an mos timing simulator , 1975 .

[4]  Randal E. Bryant,et al.  A Switch-Level Model and Simulator for MOS Digital Systems , 1984, IEEE Transactions on Computers.

[5]  Michael A. Harrison,et al.  Introduction to switching and automata theory , 1965 .

[6]  John K. Ousterhout Crystal: a Timing Analyzer for nMOS VLSI Circuits , 1983 .

[7]  John P. Hayes,et al.  An Experimental MOS Fault Simulation Program CSASIM , 1984, 21st Design Automation Conference Proceedings.

[8]  J. Hayes A unified switching theory with applications to VLSI design , 1982, Proceedings of the IEEE.

[9]  Randal E. Bryant A SWITCH-LEVEL SIMULATION MODEL FOR INTEGRATED LOGIC CIRCUITS , 1981 .

[10]  Piet Stevens,et al.  BIMOS, an MOS oriented multi-level logic simulator , 1983, 20th Design Automation Conference Proceedings.

[11]  R. R. Shively,et al.  Cascading Transmission Gates to Enhance Multiplier Performance , 1984, IEEE Transactions on Computers.

[12]  John P. Hayes A Logic Design Theory for VLSI , 1981 .

[13]  John P. Hayes,et al.  Pseudo-Boolean Logic Circuits , 1986, IEEE Transactions on Computers.