论文信息 - A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range

A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range

This paper describes the architecture and the IC implementation of a direct digital frequency synthesizer (DDFS) that is based on an angle rotation algorithm (similar to CORDIC). It is shown that the architecture can be implemented as a multiplierless, feedforward, and easily pipelineable datapath. A prototype IC has been designed, fabricated in 1.0-/spl mu/m CMOS, and tested. The IC produces 16-b sine and cosine outputs with a spurious-free dynamic range of more than 100 dBc. A 36-b frequency control word gives a tuning resolution of 0.0015 Hz at a 100-MHz sampling rate.

[1] Venceslav F. Kroupa. A Digital Frequency Synthesizer , 1999 .

[2] S. Mehrgardt. Noise spectra of digital sine-generators using the table-lookup method , 1983 .

[3] H. Samueli,et al. An Analysis of the Output Spectrum of Direct Digital Frequency Synthesizers in the Presence of Phase-Accumulator Truncation , 1987, 41st Annual Symposium on Frequency Control.

[4] R. J. van de Plassche,et al. A 540-MHz 10-b polar-to-Cartesian converter , 1991 .

[5] H. Samueli,et al. A 150-MHz Direct Digital Frequency Synthesizer In 1.25/spl mu/m CMOS With -90dBc Spurious Performance , 1991 .

[6] Michael J. Flanagan,et al. Spur-reduced digital sinusoid synthesis , 1993, IEEE Trans. Commun..

[7] Jack E. Volder. The CORDIC Trigonometric Computing Technique , 1959, IRE Trans. Electron. Comput..

[8] Norbert J. Fliege,et al. Complex digital oscillators and FSK modulators , 1992, IEEE Trans. Signal Process..