Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia

The paradigm and the usage of CMOS are changing, and so are the requirements at all levels, from transistor to an entire CMOS system. The traditional drivers, such as speed and density of integration, are subject to other prerogatives related to variability, manufacturability, power consumption/dissipation (mobile products!), mix of varied digital and analog/RF functions (system-on-chip integration), etc. Controllability of variations and static leakage will add to, and in certain products prevail, over speed and density. Implications at all levels are multiple and are more diverse than just speed and smallness. The goal of the authors has been to see the problem globally from the product level and to place its components in their true proportions. Therefore, we will start with drawing the product-level picture and placing it in a historical perspective. Next, we will review the state of the art, the requirements, and solutions at the level of materials, transistor, and technology. Detailed analysis and potential solutions for prolonging CMOS as the leading information technology are presented in this paper.

[1]  Y. Yeo,et al.  25 nm CMOS Omega FETs , 2002, Digest. International Electron Devices Meeting,.

[2]  Toshitsugu Sakamoto,et al.  Observation of source-to-drain direct tunneling current in 8 nm gate electrically variable shallow junction metal–oxide–semiconductor field-effect transistors , 2000 .

[3]  K. Natori Ballistic metal-oxide-semiconductor field effect transistor , 1994 .

[4]  T. Skotnicki,et al.  16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[5]  J. Colinge,et al.  Silicon-on-insulator 'gate-all-around device' , 1990, International Technical Digest on Electron Devices.

[6]  V.V. Zhirnov,et al.  Future devices for information processing , 2005, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..

[7]  T. Skotnicki,et al.  Requirements for ultra-thin-film devices and new materials on CMOS roadmap , 2003, 2003 IEEE International Conference on SOI.

[8]  Anna W. Topol,et al.  Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[9]  S. Samavedam,et al.  Fermi level pinning at the polySi/metal oxide interface , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

[10]  Donggun Park,et al.  Highly Manufacturable Single-Bridge-Channel MOSFET (SBCFET) , 2006, 2006 IEEE International Conference on IC Design and Technology.

[11]  S. Kosonocky,et al.  Fluctuation limits & scaling opportunities for CMOS SRAM cells , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[12]  A. Ogura,et al.  Sub-10-nm planar-bulk-CMOS devices using lateral junction control , 2003, IEEE International Electron Devices Meeting 2003.

[13]  T. Skotnicki,et al.  A new backscattering model giving a description of the quasi-ballistic transport in nano-MOSFET , 2005, IEEE Transactions on Electron Devices.

[14]  Sorin Cristoloveanu,et al.  Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture , 2002 .

[15]  M. Lundstrom,et al.  Essential physics of carrier transport in nanoscale MOSFETs , 2002 .

[16]  T. Skotnicki,et al.  Optimal Scaling Methodologies and Transistor Performance , 2005 .

[17]  G. Ghibaudo,et al.  Investigations on possible occurrence of ballistic transport in different NMOS architectures , 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

[18]  K. Saraswat,et al.  Investigation of the performance limits of III-V double-gate n-MOSFETs , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[19]  T. Skotnicki,et al.  High-Performance High-$K$/Metal Planar Self-Aligned Gate-All-Around CMOS Devices , 2008, IEEE Transactions on Nanotechnology.

[20]  M. Jurczak,et al.  Silicon-on-Nothing (SON)-an innovative process for advanced CMOS , 2000 .

[21]  J. Welser,et al.  Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors , 1994, IEEE Electron Device Letters.

[22]  Nicolas Loubet,et al.  A Novel Self Aligned Design Adapted Gate All Around (SADAGAA) MOSFET including two stacked Channels : A High Co-Integration Potential , 2006 .

[23]  A. Chou,et al.  Hybrid-orientation technology (HOT): opportunities and challenges , 2006, IEEE Transactions on Electron Devices.

[24]  J.R. Hauser,et al.  Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors , 1999, IEEE Electron Device Letters.

[25]  H.-S.P. Wong,et al.  Extreme scaling with ultra-thin Si channel MOSFETs , 2002, Digest. International Electron Devices Meeting,.

[26]  清水 昭博,et al.  Local Mechanical-Stress Control(LMC): A New Technique for CMOS-Performance Enhancement , 2002 .

[27]  T. Skotnicki,et al.  Totally silicided (CoSi/sub 2/) polysilicon: a novel approach to very low-resistive gate (/spl sim/2/spl Omega///spl square/) without metal CMP nor etching , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[28]  G. Dewey,et al.  Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[29]  J. Conner,et al.  Performance and Variability Comparisons between Multi-Gate FETs and Planar SOI Transistors , 2006, 2006 International Electron Devices Meeting.

[30]  E.A. Fitzgerald,et al.  Optimized strained Si/strained Ge dual-channel heterostructures for high mobility P- and N-MOSFETs , 2003, IEEE International Electron Devices Meeting 2003.

[31]  Y. Yeo,et al.  Enhanced performance in 50 nm N-MOSFETs with silicon-carbon source/drain regions , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[32]  J. Koga,et al.  Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[33]  T. Mizuno,et al.  Experimental Study Of Threshold Voltage Fluctuations Using An 8k MOSFET's Array , 1993, Symposium 1993 on VLSI Technology.

[34]  Anantha Chandrakasan,et al.  Design methodology for fine-grained leakage control in MTCMOS , 2003, ISLPED '03.

[35]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.

[36]  Donggun Park,et al.  Sub-25nm single-metal gate CMOS multi-bridge-channel MOSFET (MBCFET) for high performance and low power application , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[37]  Chang Woo Oh,et al.  A novel sub-50 nm multi-bridge-channel MOSFET (MBCFET) with extremely high performance , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[38]  D. Delille,et al.  Highly performant double gate MOSFET realized with SON process , 2003, IEEE International Electron Devices Meeting 2003.

[39]  Kok Wai Wong,et al.  Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation , 2002, Digest. International Electron Devices Meeting,.

[40]  B. Ghyselen,et al.  Performance Enhancement of MUGFET Devices Using Super Critical Strained-SOI (SC-SSOI) and CESL , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[41]  Ying Zhang,et al.  Issues in NiSi-gated FDSOI device integration , 2003, IEEE International Electron Devices Meeting 2003.

[42]  X. Garros,et al.  /spl Omega/FETs transistors with TiN metal gate and HfO/sub 2/ down to 10nm , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[43]  A. Chou,et al.  High performance CMOS fabricated on hybrid substrate with different crystal orientations , 2003, IEEE International Electron Devices Meeting 2003.

[44]  L.T. Clark,et al.  Reverse-body bias and supply collapse for low effective standby power , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[45]  T. Skotnicki,et al.  A new punchthrough current model based on the voltage-doping transformation , 1988 .

[46]  H. Nayfeh,et al.  Strained silicon MOSFET technology , 2002, Digest. International Electron Devices Meeting,.

[47]  S. Locorotondo,et al.  CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[48]  T. Skotnicki,et al.  Refinement of the Subthreshold Slope Modeling for Advanced Bulk CMOS Devices , 2007, IEEE Transactions on Electron Devices.

[49]  A. Chandrakasan,et al.  MTCMOS sequential circuits , 2001, Proceedings of the 27th European Solid-State Circuits Conference.

[50]  H. Iwai Future semiconductor manufacturing: challenges and opportunities , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[51]  T. Skotnicki,et al.  The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance , 2005, IEEE Circuits and Devices Magazine.

[52]  Chun-Yung Sung,et al.  High performance cmos bulk technology using direct silicon bond (dsb) mixed crystal orientation substrates , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[53]  K. Ishibashi,et al.  Adaptive Threshold-Voltage CMOS with Forward Bias , 2000 .

[54]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .

[55]  P. Dollfus,et al.  On the ballistic transport in nanometer-scaled DG MOSFETs , 2003, IEEE Transactions on Electron Devices.

[56]  Stephane Monfray,et al.  Emerging silicon-on-nothing (SON) devices technology , 2004 .

[57]  M.-R. Lin,et al.  Transistors with dual work function metal gates by single full silicidation (FUSI) of polysilicon gates , 2002, Digest. International Electron Devices Meeting,.

[58]  T. Skotnicki,et al.  Analytical study of punchthrough in buried channel P-MOSFETs , 1989 .

[59]  Mark C. Johnson,et al.  Leakage control with efficient use of transistor stacks in single threshold CMOS , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[60]  V. Fiori,et al.  Performance boost of scaled Si PMOS through novel SiGe stressor for HP CMOS , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[61]  J. Robertson,et al.  Band Alignments of High-K Dielectrics on Si and Pt , 1999 .

[62]  C. Mazure,et al.  Impact of Advanced SOI Substrates on Device Architecture and Design , 2006, 2006 IEEE International Conference on IC Design and Technology.

[63]  T. Skotnicki,et al.  SON (silicon on nothing)-a new device architecture for the ULSI era , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

[64]  M. Vinet,et al.  Bonded planar double-metal-gate NMOS transistors down to 10 nm , 2005, IEEE Electron Device Letters.

[65]  C. Mazure Advanced Substrate Engineering for the Nanotechnology Era , 2006, 2006 International Symposium on VLSI Technology, Systems, and Applications.

[66]  P. Bai,et al.  A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell , 2002, Digest. International Electron Devices Meeting,.

[67]  D. Hisamoto,et al.  A fully depleted lean-channel transistor (DELTA)-a novel vertical ultrathin SOI MOSFET , 1990, IEEE Electron Device Letters.

[68]  T. Skotnicki,et al.  50 nm-Gate All Around (GAA)-Silicon On Nothing (SON)-devices: a simple way to co-integration of GAA transistors within bulk MOSFET process , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[69]  K. Steinhubl Design of Ion-Implanted MOSFET'S with Very Small Physical Dimensions , 1974 .

[70]  M. Silberstein,et al.  A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors , 2003, IEEE International Electron Devices Meeting 2003.

[71]  Sung Min Kim,et al.  122 Mb High Speed SRAM Cell with 25 nm Gate Length Multi-Bridge-Channel MOSFET (MBCFET) on Bulk Si Substrate , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[72]  T. Skotnicki,et al.  The voltage-doping transformation: a new approach to the modeling of MOSFET short-channel effects , 1988, IEEE Electron Device Letters.

[73]  F. Balestra,et al.  Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance , 1987, IEEE Electron Device Letters.

[74]  T. Skotnicki,et al.  Physics of the Subthreshold Slope - Initial Improvement and Final Degradation in Short CMOS Devices , 2002, 32nd European Solid-State Device Research Conference.

[75]  P. Abramowitz,et al.  Dual-metal gate CMOS with HfO2 gate dielectric , 2002, Digest. International Electron Devices Meeting,.

[76]  M. Haond,et al.  SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi/sub 2/) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels , 2002, Digest. International Electron Devices Meeting,.

[77]  Sani R. Nassif,et al.  High Performance CMOS Variability in the 65nm Regime and Beyond , 2006, 2007 IEEE International Electron Devices Meeting.

[78]  J. Hutchby,et al.  THE ROAD TO THE END OF CMOS SCALING , 2004 .

[79]  T. Skotnicki,et al.  Study on Enhanced Performance in NMOSFETs on Strained Silicon , 1999, 29th European Solid-State Device Research Conference.