Advanced Junction Engineering for 60nm-CMOS Transistors

In this paper, we evaluate new concepts in the ultra shallow junction engineering such as Ultra Low Energy (ULE) and Plasma Doping Implant (PLAD) and fast ramp-up Spike Annealing after integration into planar 60nm-transistors. Excellent results in terms of SCE and DIBL reduction are obtained for As implant at 1 keV and B PLAD implant for nMOS and pMOS devices respectively. Further improvement can be obtained by using Levitor Spike Annealing. Future work has to be focussed on the optimisation of the transistor performances.