Two-phase charge-coupled device

A charge-transfer efficiency of 99.99% per stage was achieved in the fat-zero mode of operation of 64- and 128-stage two-phase charge-coupled shift registers at 1.0-MHz clock frequency. The experimental two-phase charge-coupled shift registers were constructed in the form of polysilicon gates overlapped by aluminum gates. The unidirectional signal flow was accomplished by using n-type substrates with 0.5 to 1.0 ohm-cm resistivity in conjunction with a channel oxide thickness of 1000 A for the polysilicon gates and 3000 A for the aluminum gates. The operation of the tested shift registers with fat zero is in good agreement with the free-charge transfer characteristics expected for the tested structures. The charge-transfer losses observed when operating the experimental shift registers without the fat zero are attributed to fast interface state trapping. The analytical part of the report contains a review backed up by an extensive appendix of the free-charge transfer characteristics of CCD's in terms of thermal diffusion, self-induced drift, and fringing field drift. Also, a model was developed for the charge-transfer losses resulting from charge trapping by fast interface states. The proposed model was verified by the operation of the experimental two-phase charge-coupled shift registers.