RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience

[1]  Muhammad Shafique,et al.  Reliable software for unreliable hardware: Embedded code generation aiming at reliability , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[2]  Karthikeyan Sankaralingam,et al.  Relax: an architectural framework for software recovery of hardware faults , 2010, ISCA.

[3]  Michael Engel,et al.  Classification-Based Improvement of Application Robustness and Quality of Service in Probabilistic Computer Systems , 2012, ARCS.

[4]  Hans-Joachim Wunderlich.  Models in Hardware Testing , 2010 .

[5]  Fernanda Gusmão de Lima Kastensmidt,et al.  Generation and Propagation of Single Event Transients in CMOS Circuits , 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.

[6]  Shubu Mukherjee,et al.  Architecture Design for Soft Errors , 2008 .

[7]  Norbert Wehn,et al.  Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience , 2014, Microelectron. Reliab..

[8]  Marco Platzner,et al.  Design and architectures for dependable embedded systems , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[9]  Lara Dolecek,et al.  Underdesigned and Opportunistic Computing in Presence of Hardware Variability , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Muhammad Shafique,et al.  Reliability-Driven Software Transformations for Unreliable Hardware , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Sanghyeon Baeg,et al.  Memory Reliability Model for Accumulated and Clustered Soft Errors , 2011, IEEE Transactions on Nuclear Science.

[12]  David R. Kaeli,et al.  Eliminating microarchitectural dependency from Architectural Vulnerability , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[13]  Muhammad Shafique,et al.  Leveraging variable function resilience for selective software reliability on unreliable hardware , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[14]  Michael Engel,et al.  Improving the fault resilience of an H.264 decoder using static analysis methods , 2013, TECS.

[15]  Muhammad Shafique,et al.  Reliable code generation and execution on unreliable hardware under joint functional and timing reliability considerations , 2013, 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS).

[16]  Alessandro Savino,et al.  RIIF-2: Toward the next generation reliability information interchange format , 2016, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS).

[17]  B.L. Bhuva,et al.  Soft Error Considerations for Multicore Microprocessor Design , 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.

[18]  Norbert Wehn,et al.  Circuit Resilience Roadmap , 2015 .

[19]  Rüdiger Kapitza,et al.  Multi-layer software reliability for unreliable hardware , 2015, it Inf. Technol..

[20]  Ulf Schlichtmann,et al.  Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling , 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

[21]  Kaushik Roy,et al.  A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications , 2011, IEEE Transactions on Circuits and Systems for Video Technology.

[22]  A soft error rate analysis (SERA) methodology , 2006, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[23]  Muhammad Shafique,et al.  Exploiting program-level masking and error propagation for constrained reliability optimization , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[24]  Hans-Joachim Wunderlich,et al.  Generalized Fault Modeling for Logic Diagnosis , 2010 .

[25]  Edward J. McCluskey,et al.  Detecting bridging faults with stuck-at test sets , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[26]  Norbert Wehn,et al.  A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience , 2013, IEEE Micro.

[27]  Adrian Evans,et al.  RIIF - Reliability information interchange format , 2012, 2012 IEEE 18th International On-Line Testing Symposium (IOLTS).

[28]  Nicholas P. Carter,et al.  CCC visioning study: system-level cross-layer cooperation to achieve predictable systems from unpredictable components , 2011 .

[29]  Tommy Kuhn,et al.  Testing reliability techniques for SoCs with fault tolerant CGRA by using live FPGA fault injection , 2013, 2013 International Conference on Field-Programmable Technology (FPT).

[30]  Michael Engel,et al.  Unreliable yet useful - reliability annotations for data in cyber-physical systems , 2011, GI-Jahrestagung.

[31]  Mohammad Modarres,et al.  Reliability engineering and risk analysis : a practical guide , 2016 .

[32]  Farzan Fallah,et al.  Overcoming post-silicon validation challenges through Quick Error Detection (QED) , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[33]  Julius Ziegler,et al.  Making Bertha Drive—An Autonomous Journey on a Historic Route , 2014, IEEE Intelligent Transportation Systems Magazine.

[34]  Hsiu-Ming Chang,et al.  Time-Multiplexed Online Checking , 2011, IEEE Transactions on Computers.

[35]  S. S. Chung,et al.  Spreading Diversity in Multi-cell Neutron-Induced Upsets with Device Scaling , 2006, IEEE Custom Integrated Circuits Conference 2006.