A Constraint-driven Placement Methodology For Analog Integrated Circuits

A new constraint-driven methodology for the placeinent of analog IC's is described. Electrical performance specifications are automatically translated into constraints on the layout parasitics. These constraints and the seiisiitivity iiiforinatioii of the circuit are then used to control a Simulated Annealingbased placement algorithm. At each step of the annealing a fast check on performance degradations is performed to guarantee that the tool has the necessary robur,tness.

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