Silicon‐on‐insulator MOSFETs models in analog/RF domain

Several physical phenomena specific to silicon-on-insulator metal-oxide-semiconductor field-effect transistors, such as floating body effects, self-heating, and substrate coupling, are described and modeled. Small-signal equivalent circuit of ultra-thin body and thin buried oxide and fin field effect transistor FinFET are extracted, and their radio frequency figures of merit as well as their advantages and limitations are presented. We demonstrate the importance of performing wideband characterization at the early stage of the technology development in order to identify the device weaknesses and come up with technological solutions to overcome those. With the ongoing downscaling of the metal-oxide-semiconductor devices, the surrounding of the transistor, that is, the contacts, the access lines, and the substrate, starts to play a major role on the transistor behavior. There is an urgent need to develop adequate models for the new generation of devices valid over a wide frequency band. © 2013 The Authors. INTERNATIONAL JOURNAL OF NUMERICAL MODELLING: ELECTRONIC NETWORKS, DEVICES AND FIELDS Published by John Wiley & Sons, Ltd.

[1]  J-P Raskin,et al.  RF Harmonic Distortion of CPW Lines on HR-Si and Trap-Rich HR-Si Substrates , 2012, IEEE Transactions on Electron Devices.

[2]  T. Hiramoto,et al.  Impact of Parameter Variations and Random Dopant Fluctuations on Short-Channel Fully Depleted SOI MOSFETs With Extremely Thin BOX , 2007, IEEE Electron Device Letters.

[3]  Enrico Sangiorgi,et al.  Reduced Self-Heating by Strained Silicon Substrate Engineering , 2007 .

[4]  Denis Flandre,et al.  Impact of self-heating and substrate effects on small-signal output conductance in UTBB SOI MOSFETs , 2012 .

[5]  Ying-Che Tseng,et al.  AC floating body effects and the resultant analog circuit issues in submicron floating body and body-grounded SOI MOSFET's , 1999 .

[6]  P. Kulkarni,et al.  Extremely thin SOI (ETSOI) technology: Past, present, and future , 2010, 2010 IEEE International SOI Conference (SOI).

[7]  Stephane Monfray,et al.  Requirements for ultra-thin-film devices and new materials for the CMOS roadmap , 2004 .

[8]  Jean-Pierre Colinge,et al.  Multiple-gate SOI MOSFETs: device design guidelines , 2002 .

[9]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.

[10]  Denis Flandre,et al.  Electrical characterization of true Silicon-On-Nothing MOSFETs fabricated by Si layer transfer over a pre-etched cavity , 2007 .

[11]  N. Fel,et al.  A New Approach for SOI Devices Small-Signal Parameters Extraction , 2000 .

[12]  A. G. Martinez-Lopez,et al.  Fringing gate capacitance model for triple-gate FinFET , 2013, 2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

[13]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .

[14]  R. Howes,et al.  A small-signal model for the frequency-dependent drain admittance in floating-substrate MOSFET's , 1992 .

[15]  Dominique Schreurs,et al.  A comprehensive review on microwave FinFET modeling for progressing beyond the state of art , 2013 .

[16]  C.R. Cleavelin,et al.  Body effect in tri- and pi-gate SOI MOSFETs , 2004, IEEE Electron Device Letters.

[17]  C. Fiegna,et al.  Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation , 2008, IEEE Transactions on Electron Devices.

[18]  F. Danneville,et al.  Optimization of RF Performance of Metallic Source/Drain SOI MOSFETs Using Dopant Segregation at the Schottky Interface , 2009, IEEE Electron Device Letters.

[19]  Jean-Pierre Raskin,et al.  New RF extrinsic resistances extraction procedure for deep-submicron MOS transistors , 2010 .

[20]  K. F. Lee,et al.  Impact of distributed gate resistance on the performance of MOS devices , 1994 .

[21]  W. Redman-White,et al.  Identification of thermal and electrical time constants in SOIMOSFETS from small signal measurements , 1993, ESSDERC '93: 23rd European solid State Device Research Conference.

[22]  Jean-Pierre Raskin,et al.  Direct extraction of the series equivalent circuit parameters for the small-signal model of SOI MOSFETs , 1997 .

[23]  K. Endo,et al.  Modeling and Analysis of Self-Heating in FinFET Devices for Improved Circuit and EOS/ESD Performance , 2007, 2007 IEEE International Electron Devices Meeting.

[24]  D. A. Antoniadis,et al.  Measurement and modeling of self-heating effects in SOI nMOSFETs , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[25]  B. Jagannathan,et al.  Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications , 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

[26]  F. Danneville,et al.  What are the limiting parameters of deep-submicron MOSFETs for high frequency applications? , 2003, IEEE Electron Device Letters.

[27]  Jean-Pierre Raskin,et al.  Mobility degradation and transistor asymmetry impact on field effect transistor access resistances extraction , 2011 .

[28]  Pin Su,et al.  Studying the impact of gate tunneling on dynamic behaviors of partially-depleted SOI CMOS using BSIMPD , 2002, Proceedings International Symposium on Quality Electronic Design.

[29]  Niccolò Rinaldi,et al.  Small-signal operation of semiconductor devices including self-heating, with application to thermal characterization and instability analysis , 2001 .

[30]  Very low effective Schottky barrier height for erbium disilicide contacts on n-Si through arsenic segregation , 2011, 1110.5461.

[31]  S. Samavedam,et al.  Analysis of parasitic resistance in double gate FinFETs with different fin lengths , 2011, IEEE 2011 International SOI Conference.

[32]  Sorin Cristoloveanu,et al.  Silicon on insulator technologies and devices: from present to future , 2001 .

[34]  Sorin Cristoloveanu,et al.  Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture , 2002 .

[35]  Guido Groeseneken,et al.  Identifying the Bottlenecks to the RF Performance of FinFETs , 2010, 2010 23rd International Conference on VLSI Design.

[36]  G. Dambrine,et al.  A new method for determining the FET small-signal equivalent circuit , 1988 .

[37]  Sorin Cristoloveanu,et al.  Advanced SOI MOSFETs with buried alumina and ground plane: self-heating and short-channel effects , 2004 .

[38]  Denis Flandre,et al.  Substrate effect on the output conductance frequency response of SOI MOSFETs (inited paper) , 2007 .

[39]  O. Faynot,et al.  Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below , 2010, 2009 Proceedings of ESSCIRC.

[40]  V. Kilchytska,et al.  Frequency Variation of the Small-Signal Output Conductance of Decananometer MOSFETs Due to Substrate Crosstalk , 2007, IEEE Electron Device Letters.

[41]  J.-P. Raskin,et al.  Characterization of the Body Node in PD SOI MOSFETs Using Multiport VNA Measurements , 2007, IEEE Transactions on Electron Devices.

[42]  S. Maegawa,et al.  Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[43]  D. Flandre,et al.  Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs , 2003, IEEE Electron Device Letters.

[44]  C. Merckling,et al.  Germanium for advanced CMOS anno 2009: a SWOT analysis , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[45]  F. Andrieu,et al.  Comparison of small-signal output conductance frequency dependence in UTBB SOI MOSFETs with and without ground plane , 2011, IEEE 2011 International SOI Conference.

[46]  J. Raskin,et al.  Radio-Frequency Study of Dopant-Segregated n-Type SB-MOSFETs on Thin-Body SOI , 2010, IEEE Electron Device Letters.

[47]  Denis Flandre,et al.  FinFET analogue characterization from DC to 110 GHz , 2005 .

[48]  O. Rozeau,et al.  Extra-low parasitic gate-to-contacts capacitance architecture for sub-14 nm transistor nodes , 2014 .

[49]  B. Jagannathan,et al.  Record RF performance of 45-nm SOI CMOS Technology , 2007, 2007 IEEE International Electron Devices Meeting.

[50]  S. Okhonin,et al.  A capacitor-less 1T-DRAM cell , 2002, IEEE Electron Device Letters.

[51]  J.-P. Raskin,et al.  Dependence of finFET RF performance on fin width , 2006, Digest of Papers. 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

[52]  Bart Vandevelde,et al.  3D technology roadmap and status , 2011, 2011 IEEE International Interconnect Technology Conference.

[53]  A. Mercha,et al.  "Linear kink effect" induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETS , 2003 .

[54]  Denis Flandre,et al.  High frequency degradation of body-contacted PD SOI MOSFET output conductance , 2005 .

[55]  Denis Flandre,et al.  Substrate crosstalk reduction using SOI technology , 1997 .

[56]  J. Raskin,et al.  RF Performance of a Commercial SOI Technology Transferred Onto a Passivated HR Silicon Substrate , 2008, IEEE Transactions on Electron Devices.

[57]  J. Raskin,et al.  Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling , 1998 .

[58]  Chenming Hu,et al.  SOI thermal impedance extraction methodology and its significance for circuit simulation , 2001 .

[59]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[60]  Mansun Chan,et al.  Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs , 2007, IEEE Transactions on Electron Devices.

[61]  Jean-Pierre Raskin Wideband characterization of SOI materials and devices , 2007 .

[62]  P. Bai,et al.  A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell , 2002, Digest. International Electron Devices Meeting,.

[63]  Jean-Pierre Raskin,et al.  RF extraction of self-heating effects in FinFETs of various geometries , 2011, 2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

[64]  G. Pailloncy,et al.  High-Frequency Performance of Schottky Source/Drain Silicon pMOS Devices , 2008, IEEE Electron Device Letters.

[65]  D. Flandre,et al.  Substrate Effects on the Small-Signal Characteristics of SOI MOSFETs , 2002, 32nd European Solid-State Device Research Conference.

[66]  A. Toffoli,et al.  Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond , 2010, 2010 Symposium on VLSI Technology.

[67]  Mark J. W. Rodwell,et al.  Submicron scaling of HBTs , 2001 .

[68]  O. Rozeau,et al.  Wideband characterization of body-accessed PD SOI MOSFETs with multiport measurements , 2005, 2005 IEEE International SOI Conference Proceedings.

[69]  D. Vasileska,et al.  Self-Heating Effects in Nanoscale FD SOI Devices: The Role of the Substrate, Boundary Conditions at Various Interfaces, and the Dielectric Material Type for the BOX , 2009, IEEE Transactions on Electron Devices.

[70]  S. C. Wang,et al.  W-band high efficiency InP-based power HEMT with 600 GHz f/sub max/ , 1995 .

[71]  Chenming Hu,et al.  Ultrathin-body SOI MOSFET for deep-sub-tenth micron era , 2000, IEEE Electron Device Letters.

[72]  Denis Flandre,et al.  Comparison of TiSi2 , CoSi2, and NiSi for Thin‐Film Silicon‐on‐Insulator Applications , 1997 .

[73]  Jeffrey Bokor,et al.  Extremely scaled silicon nano-CMOS devices , 2003, Proc. IEEE.

[74]  A. Asenov,et al.  High Mobility III-V MOSFETs For RF and Digital Applications , 2007, 2007 IEEE International Electron Devices Meeting.

[75]  Eric Pop,et al.  Heat Generation and Transport in Nanometer-Scale Transistors , 2006, Proceedings of the IEEE.

[76]  G.D.J. Smit,et al.  Experimental assessment of self-heating in SOI FinFETs , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[77]  V. Kilchytska,et al.  Perspective of FinFETs for analog applications , 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

[78]  D. Lederer,et al.  New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity , 2005, IEEE Electron Device Letters.

[79]  T. Skotnicki,et al.  Requirements for ultra-thin-film devices and new materials on CMOS roadmap , 2003, 2003 IEEE International Conference on SOI.

[80]  A. Gharsallah,et al.  Ultrawide Frequency Range Crosstalk Into Standard and Trap-Rich High Resistivity Silicon Substrates , 2011, IEEE Transactions on Electron Devices.

[81]  O. Faynot,et al.  Efficient multi-VT FDSOI technology with UTBOX for low power circuit design , 2010, 2010 Symposium on VLSI Technology.

[82]  D. Vasileska,et al.  Modeling Thermal Effects in Nanodevices , 2008 .

[83]  Gerard Ghibaudo,et al.  Analysis and modeling of self-heating effects in thin-film SOI MOSFETs as a function of temperature , 1995 .

[84]  Kee Soo Nam,et al.  A novel approach to extracting small-signal model parameters of silicon MOSFET's , 1997 .

[85]  G. Knoblinger,et al.  Self Heating Simulation of Multi-Gate FETs , 2006, 2006 European Solid-State Device Research Conference.

[86]  O. Faynot,et al.  Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel , 2010 .

[87]  O. Faynot,et al.  Ultra-thin body and BOX SOI Analog Figures of Merit , 2011 .

[88]  M. Sherony,et al.  Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

[89]  Denis Flandre,et al.  Silicon-on-Nothing MOSFETs: An efficient solution for parasitic substrate coupling suppression in SOI devices , 2008 .

[90]  Akira Matsuzawa,et al.  Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications , 2006 .

[91]  G. Pailloncy,et al.  Static and High-Frequency Behavior and Performance of Schottky-Barrier p-MOSFET Devices , 2007, IEEE Transactions on Electron Devices.

[92]  Denis Flandre,et al.  UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime , 2013 .

[93]  S. Cristoloveanu,et al.  New Mechanism of Body Charging in Partially Depleted SOI-MOSFETs with Ultra-thin Gate Oxides , 2002, 32nd European Solid-State Device Research Conference.

[94]  M. Vinet,et al.  Impact of back bias on ultra-thin body and BOX (UTBB) devices , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[95]  Enrico Sangiorgi,et al.  Simulation of self-heating effects in different SOI MOS architectures , 2009 .

[96]  W. Deal,et al.  Sub 50 nm InP HEMT Device with Fmax Greater than 1 THz , 2007, 2007 IEEE International Electron Devices Meeting.

[97]  O. Faynot,et al.  Threshold voltage in ultra thin FDSOI CMOS : Advanced triple interface model and experimental devices , 2008, 2008 9th International Conference on Ultimate Integration of Silicon.

[98]  F. Danneville,et al.  RF Small-Signal Analysis of Schottky-Barrier p-MOSFET , 2008, IEEE Transactions on Electron Devices.

[99]  O. Faynot,et al.  Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit , 2012 .

[100]  X. Garros,et al.  FDSOI devices with thin BOX and ground plane integration for 32nm node and below , 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

[101]  O. Rozeau,et al.  HF characterisation of sub-100nm UTB-FDSOI with TiN/HfO2 gate stack , 2008, 2008 9th International Conference on Ultimate Integration of Silicon.

[102]  Schottky barrier lowering with the formation of crystalline Er silicide on n-Si upon thermal annealing , 2009, 1110.5506.

[103]  W. Lee,et al.  A novel CVD-SiBCN Low-K spacer technology for high-speed applications , 2008, 2008 Symposium on VLSI Technology.

[104]  D. Flandre,et al.  AC behavior of gate-induced floating body effects in ultrathin oxide PD SOI MOSFETs , 2004, IEEE Electron Device Letters.

[105]  M. Jurczak,et al.  Silicon-on-Nothing (SON)-an innovative process for advanced CMOS , 2000 .

[106]  Jean-Philippe Noel,et al.  32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[107]  Katsuyuki Sakuma,et al.  Three-dimensional silicon integration , 2008, IBM J. Res. Dev..

[108]  R. Tsuchiya,et al.  Comprehensive study on vth variability in silicon on Thin BOX (SOTB) CMOS with small random-dopant fluctuation: Finding a way to further reduce variation , 2008, 2008 IEEE International Electron Devices Meeting.

[109]  N. Collaert,et al.  Analysis of the parasitic S/D resistance in multiple-gate FETs , 2005, IEEE Transactions on Electron Devices.

[110]  Byung-Gook Park,et al.  Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile , 2002 .

[111]  J. Raskin,et al.  Effective resistivity of fully-processed SOI substrates , 2005 .

[112]  J. Tihanyi,et al.  Influence of the floating substrate potential on the characteristics of ESFI MOS transistors , 1975 .

[113]  T. Skotnicki,et al.  Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia , 2008, IEEE Transactions on Electron Devices.

[114]  Nicolas Loubet,et al.  Ultra-Thin Body and BOX (UTBB) Device for Aggressive Scaling of CMOS Technology , 2011 .

[115]  Jean-Pierre Raskin,et al.  High-frequency performance of Schottky Barrier p-MOSFET devices , 2008 .

[116]  Martin M. Frank,et al.  Germanium channel MOSFETs: Opportunities and challenges , 2006, IBM J. Res. Dev..

[117]  F. Balestra,et al.  Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance , 1987, IEEE Electron Device Letters.

[118]  Jean-Pierre Raskin,et al.  Dynamic threshold voltage MOS in partially depleted SOI technology: a wide frequency band analysis , 2005 .

[119]  William Redman-White,et al.  Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques , 1996 .

[120]  S. Makovejev,et al.  RF Extraction of Self-Heating Effects in FinFETs , 2011, IEEE Transactions on Electron Devices.

[121]  N. Loubet,et al.  Scalability of Extremely Thin SOI (ETSOI) MOSFETs to Sub-20-nm Gate Length , 2012, IEEE Electron Device Letters.

[122]  J.-P. Raskin,et al.  Optimizing FinFET geometry and parasitics for RF applications , 2008, 2008 IEEE International SOI Conference.

[123]  Jean-Pierre Raskin,et al.  SOI technology: An opportunity for RF designers? , 2023, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test.