Graph-based dynamic analysis: Efficient characterization of dynamic timing and activity distributions

In light of increasing energy overheads required to guarantee correctness as variations increase with continued technology scaling, better-than-worst-case (BTWC) design has become a hot topic. Several BTWC design techniques utilize dynamic information like path activity when optimizing a design and rely on path-based analysis to determine the dynamic slack distribution of a workload running on a processor and subsequently optimize a design. In this paper, we show that path-based techniques are not scalable, due to the enormous number of paths in modern designs, and can also result in incorrect results. We propose a graph-based technique for performing dynamic timing and activity analysis of a workload on a processor that addresses the limitations of path-based techniques. Our tool has significantly lower runtime and memory requirements than path-based tools. Consequently, we can perform analysis for larger designs over longer time windows in a shorter amount of time. We also propose two optimizations that improve the performance of our tool.

[1]  Jiayong Le,et al.  A parametric approach for handling local variation effects in timing analysis , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[2]  Young Hwan Kim,et al.  Incremental statistical static timing analysis with gate timing yield emphasis , 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

[3]  Rajesh Gupta,et al.  Timing analysis of erroneous systems , 2014, 2014 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[4]  John Sartori,et al.  Compiling for energy efficiency on timing speculative processors , 2012, DAC Design Automation Conference 2012.

[5]  Josep Torrellas,et al.  EVAL: Utilizing processors with variation-induced timing errors , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[6]  John Sartori,et al.  Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Luca Benini,et al.  Application-Adaptive Guardbanding to Mitigate Static and Dynamic Variability , 2014, IEEE Transactions on Computers.

[8]  Jing Xin,et al.  Identifying and predicting timing-critical instructions to boost timing speculation , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[9]  Josep Torrellas,et al.  Blueshift: Designing processors for timing speculation from the ground up. , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[10]  David Blaauw,et al.  Energy-Efficient Subthreshold Processor Design , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  John Sartori,et al.  Exploiting Timing Error Resilience in Processor Architecture , 2013, TECS.

[12]  John Sartori,et al.  Recovery-driven design: A power minimization methodology for error-tolerant processor modules , 2010, Design Automation Conference.

[13]  J. Torrellas,et al.  VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects , 2008, IEEE Transactions on Semiconductor Manufacturing.

[14]  Subhasish Mitra,et al.  Testing for Transistor Aging , 2009, 2009 27th IEEE VLSI Test Symposium.

[15]  Iztok Savnik,et al.  Index Data Structure for Fast Subset and Superset Queries , 2013, CD-ARES.

[16]  K. Ravindran,et al.  First-Order Incremental Block-Based Statistical Timing Analysis , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  John Sartori,et al.  Slack redistribution for graceful degradation under voltage overscaling , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[18]  Sanghamitra Roy,et al.  Efficiently tolerating timing violations in pipelined microprocessors , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).