Improving the process variation tolerability of flip-flops for UDSM circuit design

The process variation of the ultra-deep submicron technology causes significant variation in the timing characteristics of flip-flops, and it can drop functional yield seriously, affecting system timing. This paper has two objectives. First, this paper investigates the sensitivities to process variation of four representative flip-flop architectures that are popularly used in digital circuit designs in respect of their functional robustness. Secondly, this paper proposes simple but effective methods to improve the process variation tolerability of those flip-flops. Experimental results on four benchmark flip-flops, which were optimized for minimum power-delay product, show that their variability of data-to-q delay reaches to 33.02% ∼ 46.13% and functional yield reaches to 79.93% ∼ 99.86%. Also, the experimental results clearly show that the proposed approaches improve the variability of data-to-q delay by 11.53% ∼ 44.78% and functional yield by 0.11% ∼ 24.41%.

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